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altera corporation 1 apex 20k programmable logic device family march 2004, ver. 5.1 data sheet ds-apex20k-5.1 features industry?s first programmable lo gic device (pld) incorporating system-on-a-programmable-ch ip (sopc) integration ?multicore tm architecture integrating look-up table (lut) logic, product-term logic, and embedded memory ? lut logic used for regi ster-intensive functions ? embedded system block (esb) used to implement memory functions, including fi rst-in first-out (fif o) buffers, dual-port ram, and content-addr essable memory (cam) ? esb implementation of pr oduct-term logic used for combinatorial-intensive functions high density ? 30,000 to 1.5 million typical gates (see tables 1 and 2 ) ? up to 51,840 logic elements (les) ? up to 442,368 ram bits that ca n be used without reducing available logic ? up to 3,456 product-term-based macrocells table 1. apex 20k device features note (1) feature ep20k30e ep20k60e ep20k100 ep 20k100e ep20k160e ep20k200 ep20k200e maximum system gates 113,000 162,000 263,000 263,000 404,000 526,000 526,000 typical gates 30,000 60,000 100,000 100,000 160,000 200,000 200,000 les 1,200 2,560 4,160 4,160 6,400 8,320 8,320 esbs 12 16 26 26 40 52 52 maximum ram bits 24,576 32,768 53,248 53,248 81,920 106,496 106,496 maximum macrocells 192 256 416 416 640 832 832 maximum user i/o pins 128 196 252 246 316 382 376
2 altera corporation apex 20k programmable logic device family data sheet note to tables 1 and 2 : (1) the embedded ieee std. 1149.1 joint test action group (jtag) boundary-scan circuitry contributes up to 57,000 additional gates. additional features designed for low-power operation ? 1.8-v and 2.5-v supply voltage (see table 3 ) ?multivolt tm i/o interface support to inte rface with 1.8-v, 2.5-v, 3.3-v, and 5.0-v devices (see table 3 ) ? esb offering programmable power-saving mode note to table 3 : (1) apex 20ke devices can be 5.0-v tole rant by using an external resistor. table 2. additional apex 20k device features note (1) feature ep20k300e ep20k400 ep20k 400e ep20k600e ep20k1000e ep20k1500e maximum system gates 728,000 1,052,000 1,052,000 1,537,000 1,772,000 2,392,000 typical gates 300,000 400,000 400,000 600,000 1,000,000 1,500,000 les 11,520 16,640 16,640 24,320 38,400 51,840 esbs 72 104 104 152 160 216 maximum ram bits 147,456 212,992 212,992 311,296 327,680 442,368 maximum macrocells 1,152 1,664 1,664 2,432 2,560 3,456 maximum user i/o pins 408 502 488 588 708 808 table 3. apex 20k supply voltages feature device ep20k100 ep20k200 ep20k400 ep20k30e ep20k60e ep20k100e ep20k160e ep20k200e ep20k300e EP20K400E ep20k600e ep20k1000e ep20k1500e internal supply voltage (v ccint ) 2.5 v 1.8 v multivolt i/o interface voltage levels (v ccio ) 2.5 v, 3.3 v, 5.0 v 1.8 v, 2.5 v, 3.3 v, 5.0 v (1)
altera corporation 3 apex 20k programmable logic device family data sheet flexible clock management circuitr y with up to four phase-locked loops (plls) ? built-in low-skew clock tree ? up to eight global clock signals ? clocklock ? feature reducing clock delay and skew ? clockboost ? feature providing clock multiplication and division ? clockshift tm programmable clock phase and delay shifting powerful i/o features ? compliant with peripheral component interconnect special interest group (pci sig) pci local bus specification, revision 2.2 for 3.3-v operation at 33 or 66 mhz and 32 or 64 bits ? support for high-speed external memories, including ddr sdram and zbt sram (zbt is a trademark of integrated device technology, inc.) ? bidirectional i/o performance ( t co + t su ) up to 250 mhz ? lvds performance up to 840 mbits per channel ? direct connection from i/o pins to local interconnect providing fast t co and t su times for complex logic ? multivolt i/o interface support to interface with 1.8-v, 2.5-v, 3.3-v, and 5.0-v devices (see table 3 ) ? programmable clamp to v ccio ? individual tri-state output enable control for each pin ? programmable output slew-rate control to reduce switching noise ? support for advanced i/o stan dards, including low-voltage differential signaling (lvds), lv pecl, pci-x, agp, ctt, stub- series terminated logic (s stl-3 and sstl-2), gunning transceiver logic plus (gtl+), and high-speed terminated logic (hstl class i) ? pull-up on i/o pins before and during configuration advanced interco nnect structure ? four-level hierarchical fasttrack ? interconnect structure providing fast, predictable interconnect delays ? dedicated carry chain that implem ents arithmetic functions such as fast adders, counte rs, and comparators (automatically used by software tools and megafunctions) ? dedicated cascade chain th at implements high-speed, high-fan-in logic functions (automat ically used by software tools and megafunctions) ? interleaved local interconnect allows one le to drive 29 other les through the fast local interconnect advanced packaging options ? available in a variety of packages with 144 to 1,020 pins (see tables 4 through 7 ) ? fineline bga ? packages maximize bo ard space efficiency advanced software support ? software design support and automatic place-and-route provided by the altera ? quartus ? ii development system for
4 altera corporation apex 20k programmable logic device family data sheet windows-based pcs, sun sparcstations, and hp 9000 series 700/800 workstations ?altera megacore ? functions and altera megafunction partners program (ampp sm ) megafunctions ? nativelink tm integration with popula r synthesis, simulation, and timing analysis tools ? quartus ii signaltap ? embedded logic analyzer simplifies in-system design evaluation by giving access to internal nodes during device operation ? supports popular revision-control software packages including pvcs, revision control system (rcs), and source code control system (sccs ) table 4. apex 20k qfp, bga & pga package options & i/o count notes (1) , (2) device 144-pin tqfp 208-pin pqfp rqfp 240-pin pqfp rqfp 356-pin bga 652-pin bga 655-pin pga ep20k30e 92 125 ep20k60e 92 148 151 196 ep20k100 101 159 189 252 ep20k100e 92 151 183 246 ep20k160e 88 143 175 271 ep20k200 144 174 277 ep20k200e 136 168 271 376 ep20k300e 152 408 ep20k400 502 502 EP20K400E 488 ep20k600e 488 ep20k1000e 488 ep20k1500e 488
altera corporation 5 apex 20k programmable logic device family data sheet notes to tables 4 and 5 : (1) i/o counts include dedicated input and clock pins. (2) apex 20k device package types include thin quad flat pack (tqfp), plastic quad flat pack (pqfp), power quad flat pack (rqfp), 1.27-mm pitch ball-grid array (bga), 1.00-mm pitch fineline bga, and pin-grid array (pga) packages. (3) this device uses a thermally enhanced package, whic h is taller than the regu lar package. consult the altera device package information data sheet for detailed package size information. table 5. apex 20k fineline bga package options & i/o count notes (1) , (2) device 144 pin 324 pin 484 pin 672 pin 1,020 pin ep20k30e 93 128 ep20k60e 93 196 ep20k100 252 ep20k100e 93 246 ep20k160e 316 ep20k200 382 ep20k200e 376 376 ep20k300e 408 ep20k400 502 (3) EP20K400E 488 (3) ep20k600e 508 (3) 588 ep20k1000e 508 (3) 708 ep20k1500e 808 table 6. apex 20k qfp, bga & pga package sizes feature 144-pin tqfp 208-pin qfp 240-pin qfp 356-pin bga 652-pin bga 655-pin pga pitch (mm) 0.50 0.50 0.50 1.27 1.27 ? area (mm 2 ) 484 924 1,218 1,225 2,025 3,906 length width (mm mm) 22 22 30.4 30.4 34.9 34.9 35 35 45 45 62.5 62.5 table 7. apex 20k fineline bga package sizes feature 144 pin 324 pin 484 pin 672 pin 1,020 pin pitch (mm) 1.00 1.00 1.00 1.00 1.00 area (mm 2 ) 169 361 529 729 1,089 length width (mm mm) 13 13 19 19 23 23 27 27 33 33
6 altera corporation apex 20k programmable logic device family data sheet general description apex tm 20k devices are the first plds designed with the multicore architecture, which comb ines the strengths of lut-based and product- term-based devices with an enhanced memory structure. lut-based logic provides optimized performance and ef ficiency for data-path, register- intensive, mathematical, or digital signal processing (dsp) designs. product-term-based logic is optimized for complex combinatorial paths, such as complex state machines. lut- and product-term-based logic combined with memory functions an d a wide variety of megacore and ampp functions make the apex 20k device architecture uniquely suited for system-on-a-programmable-chip de signs. applications historically requiring a combination of lut-, product-term-, and memory-based devices can now be integrated into one apex 20k device. apex 20ke devices are a superset of apex 20k devices and include additional features such as adva nced i/o standard support, cam, additional global clocks, and enhanced clocklock clock circuitry. in addition, apex 20ke devices extend th e apex 20k family to 1.5 million gates. apex 20ke devices are denoted with an ?e? suffix in the device name (e.g., the ep20k1000e devi ce is an apex 20ke device). table 8 compares the features included in apex 20k and apex 20ke devices.
altera corporation 7 apex 20k programmable logic device family data sheet table 8. comparison of apex 20k & apex 20ke features feature apex 20k devices apex 20ke devices multicore system integrat ion full support full support signaltap logic analysis f ull support full support 32/64-bit, 33-mhz pci full compliance in -1, -2 speed grades full compliance in -1, -2 speed grades 32/64-bit, 66-mhz pci - full compliance in -1 speed grade multivolt i/o 2.5-v or 3.3-v v ccio v ccio selected for device certain devices are 5.0-v tolerant 1.8-v, 2.5-v, or 3.3-v v ccio v ccio selected block-by-block 5.0-v tolerant with use of external resistor clocklock support clock delay reduction 2 and 4 clock multiplication clock delay reduction m /( n v ) or m /( n k ) clock multiplication drive clocklock output off-chip external clock feedback clockshift lvds support up to four plls clockshift, clock phase adjustment dedicated clock and input pins six eight i/o standard support 2.5-v, 3.3-v, 5.0-v i/o 3.3-v pci low-voltage complementary metal-oxide semiconductor (lvcmos) low-voltage transis tor-to-transistor logic (lvttl) 1.8-v, 2.5-v, 3.3-v, 5.0-v i/o 2.5-v i/o 3.3-v pci and pci-x 3.3-v advanced graphics port (agp) center tap terminated (ctt) gtl+ lvcmos lvttl true-lvds and lvpecl data pins (in ep20k300e and larger devices) lvds and lvpecl signaling (in all bga and fineline bga devices) lvds and lvpecl data pins up to 156 mbps (in -1 speed grade devices) hstl class i pci-x sstl-2 class i and ii sstl-3 class i and ii memory support dual-port ram fifo ram rom cam dual-port ram fifo ram rom
8 altera corporation apex 20k programmable logic device family data sheet all apex 20k devices are reconfigurable and are 100 % tested prior to shipment. as a result, test vectors do not have to be generated for fault coverage purposes. instead, the de signer can focus on simulation and design verification. in addition, the designer do es not need to manage inventories of different application-specific integrated circuit (asic) designs; apex 20k devices can be configured on the board for the specific functionality required. apex 20k devices are configured at syst em power-up with data stored in an altera serial configur ation device or provided by a system controller. altera offers in-system programmab ility (isp)-capable epc1, epc2, and epc16 configuration devices, whic h configure apex 20k devices via a serial data stream. moreover, apex 20k devices contain an optimized interface that permits microproce ssors to configure apex 20k devices serially or in parallel, and synchron ously or asynchronously. the interface also enables microprocessors to trea t apex 20k devices as memory and configure the device by writing to a virtual memory location, making reconfiguration easy. after an apex 20k device has been co nfigured, it can be reconfigured in-circuit by resetting the device and loading new data. real-time changes can be made during system operation, enabling innovative reconfigurable computing applications. apex 20k devices are supported by the altera quartus ii development system, a single, integrated package th at offers hdl and schematic design entry, compilation and logic synthesis, full simulation and worst-case timing analysis , signaltap logic analysis, an d device configuration. the quartus ii software runs on window s-based pcs, sun sparcstations, and hp 9000 series 700/800 workstations. the quartus ii software provides native link interfaces to other industry- standard pc- and unix workstatio n-based eda tools. for example, designers can invoke the quartus ii software from within third-party design tools. furt her, the quartus ii software contains built-in optimized synthesis libraries; sy nthesis tools can use thes e libraries to optimize designs for apex 20k devices. for example, the synopsys design compiler library, supplied with the quartus ii development system, includes designware functions opti mized for the apex 20k architecture.
altera corporation 9 apex 20k programmable logic device family data sheet functional description apex 20k devices incorporate lut-b ased logic, product-term-based logic, and memory into one device. signal interconnections within apex 20k devices (as well as to and from device pins) are provided by the fasttrack ? interconnect?a series of fast, continuous row and column channels that run the entire le ngth and width of the device. each i/o pin is fed by an i/o element (ioe) located at the end of each row and column of the fasttrack interconnect. each ioe contains a bidirectional i/o buffer and a register th at can be used as either an input or output register to feed input, ou tput, or bidirectional signals. when used with a dedicated clock pin, these registers provide exceptional performance. ioes provide a variety of features, such as 3.3-v, 64-bit, 66-mhz pci compliance; jtag bst su pport; slew-rate control; and tri-state buffers. apex 20ke device s offer enhanced i/o support, including support for 1.8-v i/o, 2. 5-v i/o, lvcmos, lvttl, lvpecl, 3.3-v pci, pci-x, lvds, gtl+, sstl- 2, sstl-3, hstl, ctt, and 3.3-v agp i/o standards. the esb can implement a variety of memory functions, including cam, ram, dual-port ram, rom, and fifo functions. embedding the memory directly into the die improves performance and reduces die area compared to distributed-ram im plementations. moreover, the abundance of cascadable esbs ensu res that the apex 20k device can implement multiple wide memory bloc ks for high-density designs. the esb?s high speed ensures it can impl ement small memory blocks without any speed penalty. the abundance of esbs ensures that designers can create as many different-sized memo ry blocks as the system requires. figure 1 shows an overview of the apex 20k device. figure 1. apex 20k device block diagram lut lut lut lut lut memory memory memory memory ioe ioe ioe ioe ioe ioe ioe ioe lut lut memory memory ioe ioe product term product term lut lut memory memory ioe ioe product term product term product term product term product term product term fasttrack interconnect clock management circuitry ioes support pci, gtl+, sstl-3, lvds, and other standards. clocklock four-input lut for data path and dsp functions. product-term integration for high-speed control logic and state machines. flexible integration of embedded memory, including cam, ram, rom, fifo, and other memory functions.
10 altera corporation apex 20k programmable logic device family data sheet apex 20k devices provide two dedicated clock pins and four dedicated input pins that drive register control inputs. these signals ensure efficient distribution of high-speed, low-skew control signals. these signals use dedicated routing channels to provide short delays and low skews. four of the dedicated inputs drive four global signals. these four global signals can also be driven by internal logic, providing an ideal solution for a clock divider or internally generated asyn chronous clear signals with high fan-out. the dedicated clock pins fe atured on the apex 20k devices can also feed logic. the devices also feature clocklock and clockboost clock management circuitry. apex 20ke devices provide two additional dedicated clock pins, for a total of four dedicated clock pins. megalab structure apex 20k devices are constructed from a series of megalab tm structures. each megalab structure contains a group of logic array blocks (labs), one esb, and a megalab interconnect, which routes signals within the megalab structure. the ep20k30e device has 10 labs, ep20k60e through ep20k600e devices have 16 labs, and the ep20k1000e and ep20k1500e devices ha ve 24 labs. sign als are routed between megalab structures an d i/o pins via the fasttrack interconnect. in addition, edge labs can be driven by i/o pins through the local interconnect. figure 2 shows the megalab structure. figure 2. megalab structure esb megalab interconnect local interconnect to adjacent lab or ioes labs le1 le2 le3 le4 le5 le6 le7 le8 le9 le10 le1 le2 le3 le4 le5 le6 le7 le8 le9 le10 le1 le2 le3 le4 le5 le6 le7 le8 le9 le10
altera corporation 11 apex 20k programmable logic device family data sheet logic array block each lab consists of 10 les, the les? associated carry and cascade chains, lab control signals, and the local in terconnect. the local interconnect transfers signals between les in the sa me or adjacent labs, ioes, or esbs. the quartus ii compiler places asso ciated logic within an lab or adjacent labs, allowing the use of a fast local interconnect for high performance. figure 3 shows the apex 20k lab. apex 20k devices use an interleaved lab structure. this structure allows each le to drive two local interconnect areas. this feature minimizes use of the megalab and fasttrack in terconnect, prov iding higher performance and flexibility. each le can drive 29 other les through the fast local interconnect. figure 3. lab structure to/from adjacent lab, esb, or ioes to/from adjacent lab, esb, or ioes the 10 les in the lab are driven by two local interconnect areas. these les can drive two local interconnect areas. local interconnect les drive local megalab, row, and column interconnects. column interconnect row interconnect megalab interconnect
12 altera corporation apex 20k programmable logic device family data sheet each lab contains dedicated logic for driving control signals to its les and esbs. the control signals include clock, clock enable, asynchronous clear, asynchronous preset, asynchronous load, synchronous clear, and synchronous load signals. a maximum of six control signals can be used at a time. although synchronous load and clear signals are generally used when implementing counters, they can also be used with other functions. each lab can use two clocks and two clock enable signals. each lab?s clock and clock enable sign als are linked (e.g., any le in a particular lab using clk1 will also use clkena1 ). les with the same clock but different clock enable signals either use both clock signals in one lab or are placed into separate labs. if both the rising and falling edges of a clock are used in a lab, both lab- wide clock signals are used. the lab-wide control signals can be generated from the lab local interconnect, global signals, and dedicated clock pins. the inherent low skew of the fasttrack interconnect enables it to be used for clock distribution. figure 4 shows the lab control signal generation circuit. figure 4. lab control signal generation notes to figure 4 : (1) apex 20ke devices have four dedicated clocks. (2) the labclr1 and labclr2 signals also control asynchronous load and asynchronous preset for les within the lab. (3) the syncclr signal can be generated by the lo cal interconnect or global signals. syncclr or labclk2 (3) syncload or labclkena2 labclk1 labclkena1 labclr2 (2) labclr1 (2) dedicated clocks global signals local interconnect local interconnect local interconnect local interconnect 2 or 4 (1) 4
altera corporation 13 apex 20k programmable logic device family data sheet logic element the le, the smallest unit of logic in the apex 20k architecture, is compact and provides efficient lo gic usage. each le contai ns a four-input lut, which is a function generator that ca n quickly implement any function of four variables. in addition, each le contains a programmable register and carry and cascade chains. each le drives the local interconnect, megalab interconnect, and fast track interconnect routing structures. see figure 5 . figure 5. apex 20k logic element each le?s programmable re gister can be configured for d, t, jk, or sr operation. the register?s clock and cl ear control signals can be driven by global signals, general-purpose i/o pins, or any internal logic. for combinatorial functions, the register is bypassed and the output of the lut drives the outputs of the le. labclk1 labclk2 labclr1 labclr2 carry-in clock & clock enable select carry-out look-up table (lut) carry chain cascade chain cascade-in cascade-out to f asttrack interconnect, megalab interconnect, or local interconnect to f asttrack interconnect, megalab interconnect, or local interconnect programmable register prn clrn dq ena register bypass packed register select chip-wide reset labclkena1 labclkena2 synchronous load & clear logic lab-wide synchronous load lab-wide synchronous clear asynchronous clear/preset/ load logic data1 data2 data3 data4
14 altera corporation apex 20k programmable logic device family data sheet each le has two outputs that drive the local, megalab, or fasttrack interconnect routing structure. each output can be driven independently by the lut?s or register?s output. for example, the lut can drive one output while the register drives the other output. this feature, called register packing, improves device ut ilization because the register and the lut can be used for unrelated func tions. the le can also drive out registered and unregistered versions of the lut output. the apex 20k architecture provides two types of dedicated high-speed data paths that connect adjacent le s without using local interconnect paths: carry chains and cascade chains. a carry chain supports high-speed arithmetic functions such as counte rs and adders, whil e a cascade chain implements wide-input functions su ch as equality comparators with minimum delay. carry and cascade chains connect les 1 through 10 in an lab and all labs in the same megalab structure. carry chain the carry chain provides a very fast carry-forward function between les. the carry-in signal from a lower-order bit drives forward into the higher- order bit via the carry chain, and fe eds into both the lut and the next portion of the carry chain. this feat ure allows the apex 20k architecture to implement high-speed counters, ad ders, and comparators of arbitrary width. carry chain logic can be crea ted automatically by the quartus ii software compiler during design proces sing, or manually by the designer during design entry. parameterized functions such as library of parameterized modules (lpm) and de signware functions automatically take advantage of carry chains for the appropriate functions. the quartus ii software compiler create s carry chains longer than ten les by linking labs together automatically . for enhanced fitting, a long carry chain skips alternate labs in a megalab ? structure. a carry chain longer than one lab skips either from an even-numbered lab to the next even- numbered lab, or from an odd-numbered lab to the next odd- numbered lab. for example, the last le of the first lab in the upper-left megalab structure carries to the first le of the third lab in the megalab structure. figure 6 shows how an n -bit full adder can be implemented in n + 1 les with the carry chain. one portion of the lut generates the sum of two bits using the input signals and the carry-i n signal; the sum is routed to the output of the le. the register can be bypassed for simple adders or used for accumulator functions. another po rtion of the lut and the carry chain logic generates the carry- out signal, wh ich is routed directly to the carry- in signal of the next-hig her-order bit. the final ca rry-out signal is routed to an le, where it is driven onto the local, megalab, or fasttrack interconnect routing structures.
altera corporation 15 apex 20k programmable logic device family data sheet figure 6. apex 20k carry chain lut a1 b1 carry chain s1 le1 register a2 b2 carry chain s2 le2 register carry chain s n le n register a n b n carry chain carry-out le n + 1 register carry-in lut lut lut
16 altera corporation apex 20k programmable logic device family data sheet cascade chain with the cascade chain, the apex 20k architecture can implement functions with a very wide fan-in. adjacent luts can compute portions of a function in parallel; the cascade chain serially connects the intermediate values. the cascade chain can use a logical and or logical or (via de morgan?s inversion) to connect the outputs of adjacent les. each additional le prov ides four more inputs to the effective width of a function, with a short cascade delay. cascade chain logic can be created automatically by the quartus ii so ftware compiler during design processing, or manually by the designer during design entry. cascade chains longer than ten les are implem ented automatically by linking labs together. for enhanced fitting, a long cascade chain skips alternate labs in a megalab structur e. a cascade chain longer than one lab skips either from an even-num bered lab to the next even-numbered lab, or from an odd-numbered lab to the next odd-numbered lab. for example, the last le of the first la b in the upper-left megalab structure carries to the first le of the thir d lab in the megalab structure. figure 7 shows how the cascade function ca n connect adjacent les to form functions with a wide fan-in. figure 7. apex 20k cascade chain le1 lut le2 lut d[3..0] d[7..4] d[(4 n ? 1)..(4 n ? 4)] d[3..0] d[7..4] le n le1 le2 le n lut lut lut lut and cascade chain or cascade chain d[(4 n ? 1)..(4 n ? 4)]
altera corporation 17 apex 20k programmable logic device family data sheet le operating modes the apex 20k le can operate in on e of the following three modes: normal mode arithmetic mode counter mode each mode uses le resources differently. in each mode, seven available inputs to the le?the four data inputs from the lab local interconnect, the feedback from the programmab le register, and the carry-in and cascade-in from the previous le?are directed to different destinations to implement the desired logic function. lab-wide signals provide clock, asynchronous clear, asynchrono us preset, asynchronous load, synchronous clear, synchronous load , and clock enable control for the register. these lab-wide signals are available in all le modes. the quartus ii software, in conjunction with parameterized functions such as lpm and designware functi ons, automatically chooses the appropriate mode for co mmon functions such as counters, adders, and multipliers. if required, the design er can also create special-purpose functions that specify which le op erating mode to use for optimal performance. figure 8 shows the le operating modes.
18 altera corporation apex 20k programmable logic device family data sheet figure 8. apex 20k le operating modes notes to figure 8 : (1) les in normal mode support register packing. (2) there are two lab-wide clock enables per lab. (3) when using the carry-in in normal mode, the packed register feature is unavailable. (4) a register feedback multiplexer is available on le1 of each lab. (5) the data1 and data2 input signals can supply counter enable, up or down control, or register feedback signals for les other than the second le in an lab. (6) the lab-wide synchronous clear and lab wide sy nchronous load affect all registers in an lab. prn clrn dq 4-input lut carry-in (3) cascade-out cascade-in le-out normal mode (1) prn clrn dq cascade-out cascade-in 3-input lut carry-in 3-input lut carr y-out arithmetic mode counter mode data1 (5) data2 (5) prn clrn dq carr y-in lut 3-input 3-input lut carry-out data3 (data) cascade-out cascade-in lab-wide synchronous load (6) lab-wide synchronous clear (6) (4) le-out le-out le-out le-out le-out ena lab-wide clock enable (2) ena lab-wide clock enable (2) ena lab-wide clock enable (2) data1 data2 data1 data2 data3 data4
altera corporation 19 apex 20k programmable logic device family data sheet normal mode the normal mode is suitable for general logic applications, combinatorial functions, or wide decoding functi ons that can take advantage of a cascade chain. in normal mode, four data inputs from the lab local interconnect and the carry-in are inputs to a four-input lut. the quartus ii software compiler automat ically selects the carry-in or the data3 signal as one of the inputs to the lut. the lu t output can be combined with the cascade-in signal to form a cascade chain through the cascade-out signal. les in normal mode support packed registers. arithmetic mode the arithmetic mode is ideal for implementing adders, accumulators, and comparators. an le in arithmetic mode uses two 3-input luts. one lut computes a three-input fu nction; the other generates a carry output. as shown in figure 8 , the first lut uses the carr y-in signal and two data inputs from the lab local interconnect to generate a combinatorial or registered output. for example, when implementing an ad der, this output is the sum of three signals: data1 , data2 , and carry-in. the second lut uses the same three signals to generate a carry-out signal, thereby creating a carry chain. the arithmetic mode also supports simultaneous use of the cascade chain. les in arithmetic mode can drive out registered and unregistered versions of the lut output. the quartus ii software implements pa rameterized functions that use the arithmetic mode automatically where appropriate; the designer does not need to specify how the carry chain will be used. counter mode the counter mode offers clock enable, counter enable, synchronous up/down control, synchronous clear, and synchronous load options. the counter enable and synchronous up/d own control signals are generated from the data inputs of the lab loca l interconnect. the synchronous clear and synchronous load options are la b-wide signals that affect all registers in the lab. consequently, if any of the les in an lab use the counter mode, other les in that lab must be used as part of the same counter or be used for a combinator ial function. the qu artus ii software automatically places any registers that are not us ed by the counter into other labs.
20 altera corporation apex 20k programmable logic device family data sheet the counter mode uses two three-in put luts: one generates the counter data, and the other generates the fast carry bit. a 2-to-1 multiplexer provides synchronous loading, and another and gate provides synchronous clearing. if the cascade func tion is used by an le in counter mode, the synchronous clear or load overrides any signal carried on the cascade chain. the synchronous clear overrides the synchronous load. les in arithmetic mode can drive out registered and unregistered versions of the lut output. clear & preset logic control logic for the register?s clear and preset signals is controlled by lab-wide signals. the le directly supports an asynchronous clear function. the quartus ii software compiler can use a not -gate push-back technique to emulate an asynchronous preset. moreover, the quartus ii software compiler can use a programmable not -gate push-back technique to emulate simultaneous preset and clea r or asynchronous load. however, this technique uses three additional les per register. all emulation is performed automatically when the de sign is compiled. registers that emulate simultaneous preset and load will enter an unknown state upon power-up or when the chip -wide reset is asserted. in addition to the two clear and pr eset modes, apex 20k devices provide a chip-wide reset pin ( dev_clrn ) that resets all registers in the device. use of this pin is controlled through an option in the quartus ii software that is set before compilation. the chip-wide reset overrides all other control signals. registers using an as ynchronous preset are preset when the chip-wide reset is asserted; this effect results from the inversion technique used to implement the asynchronous preset. fasttrack interconnect in the apex 20k architecture, connections between les, esbs, and i/o pins are provided by the fasttr ack interconnect. the fasttrack interconnect is a series of continuous horizont al and vertical routing channels that traverse the device. th is global routing structure provides predictable performance, even in complex designs. in contrast, the segmented routing in fpgas requir es switch matrices to connect a variable number of routing paths, increasing the delays between logic resources and reducing performance. the fasttrack interconne ct consists of row and column interconnect channels that span the entire device . the row interconne ct routes signals throughout a row of megalab structur es; the column interconnect routes signals throughout a column of mega lab structures. when using the row and column interconnect, an le, ioe, or esb can drive any other le, ioe, or esb in a device. see figure 9 .
altera corporation 21 apex 20k programmable logic device family data sheet figure 9. apex 20k interconnect structure a row line can be driven directly by les, ioes, or esbs in that row. further, a column line can drive a row line, allowing an le, ioe, or esb to drive elements in a different row via the column and row interconnect. the row interconnect drives the megalab interconnect to drive les, ioes, or esbs in a particular megalab structure. a column line can be directly driven by les, ioes, or esbs in that column. a column line on a device?s left or right edge can also be driven by row ioes. the column line is used to rout e signals from one row to another. a column line can drive a row line; it can also drive the megalab interconnect directly, allowing faster connections between rows. figure 10 shows how the fasttrack interconnect uses the local interconnect to drive les within megalab structures. megalab megalab megalab megalab i/o i/o i/o i/o i/o i/o i/o i/o megalab megalab megalab megalab i/o megalab megalab megalab megalab i/o i/o i/o i/o i/o column interconnec t column interconnect row interconnect
22 altera corporation apex 20k programmable logic device family data sheet figure 10. fasttrack connec tion to local interconnect l a b l a b l a b l a b e s b l a b l a b i/o i/o megalab column row megalab megalab interconnect row & column interconnect drives megalab interconnect megalab interconnect drives local interconnect l a b l a b e s b row column e s b l a b
altera corporation 23 apex 20k programmable logic device family data sheet figure 11 shows the intersection of a ro w and column interconnect, and how these forms of interconnects and les drive each other. figure 11. driving the fasttrack interconnect apex 20ke devices include an enhanced interconnect structure for faster routing of input signals with high fa n-out. column i/o pins can drive the fastrow ? interconnect, which routes signals directly into the local interconnect without ha ving to drive through th e megalab interconnect. fastrow lines traverse two megalab structures. also, these pins can drive the local interconnect directly for fast setup times. on ep20k300e and larger devices, the fastrow interconnect drives the two megalabs in the top left corner, the two megalabs in the top right corner, the two megalabs in the bottom left corner, and the two megalabs in the bottom right corner. on ep20k200 e and smaller devices, fastrow interconnect drives the two megalabs on the top and the two megalabs on the bottom of the device. on all devices, the fastrow interconnect drives all local interconnect in the appropriate megalabs except the local interconnect on the side of the mega lab opposite the esb. pins using the fastrow interconnect achieve a faster set-up time, as the signal does not need to use a megalab interconnect line to reach the destination le. figure 12 shows the fastrow interconnect. row interconnect megalab interconnect le column interconnec t local interconnect
24 altera corporation apex 20k programmable logic device family data sheet figure 12. apex 20ke fastrow interconnect table 9 summarizes how various elements of the apex 20k architecture drive each other. ioe ioe ioe ioe fastrow interconnect drives local interconnect in two megalab structures megalab megalab local interconnect select vertical i/o pins drive local interconnec t and fastrow interconnect fastrow interconnect les labs
altera corporation 25 apex 20k programmable logic device family data sheet note to table 9 : (1) this connection is supported in apex 20ke devices only. product-term logic the product-term portion of the mult icore architecture is implemented with the esb. the esb can be configured to act as a block of macrocells on an esb-by-esb basis. each esb is fed by 32 inputs from the adjacent local interconnect; therefore, it can be dr iven by the megalab interconnect or the adjacent lab. also, nine esb macrocells feed back into the esb through the local interconnect for hi gher performance. dedicated clock pins, global signals, an d additional inputs from the local interconnect drive the esb control signals. in product-term mode, each esb contains 16 macrocells. each macrocell consists of two product terms and a programmable register. figure 13 shows the esb in product-term mode. table 9. apex 20k routing scheme source destination row i/o pin column i/o pin le esb local interconnect megalab interconnect row fasttrack interconnect column fasttrack interconnect fastrow interconnect row i/o pin vvvv column i/o pin vv (1) le vvvv esb vvvv local interconnect vv vv megalab interconnect v row fasttrack interconnect v v column fasttrack interconnect vv fastrow interconnect v (1)
26 altera corporation apex 20k programmable logic device family data sheet figure 13. product-term logic in esb note to figure 13 : (1) apex 20ke devices have four dedicated clocks. macrocells apex 20k macrocells can be configured individually for ei ther sequential or combinatorial logic operation. the macrocell consists of three functional blocks: the logic array, th e product-term select matrix, and the programmable register. combinatorial logic is implemented in the product terms. the product- term select matrix allocates these pr oduct terms for use as either primary logic inputs (to the or and xor gates) to implement combinatorial functions, or as parall el expanders to be used to increase the logic available to another macrocell. one product term can be inverted; the quartus ii software uses this feature to perform demorgan?s inversion for more efficient implem entation of wide or functions. the quartus ii software compiler can use a not -gate push-back technique to emulate an asynchronous preset. figure 14 shows the apex 20k macrocell. global signals dedicated clocks macrocell inputs (1-16) clk[1..0] ena[1..0] clrn[1..0] from adjacent lab megalab interconnect to row and column interconnect 2 16 32 2 2 4 2 or 4 (1) 65 local interconnect 9
altera corporation 27 apex 20k programmable logic device family data sheet figure 14. apex 20k macrocell for registered function s, each macrocell register can be programmed individually to implement d, t, jk, or sr operation with programmable clock control. the register can be bypassed for combinatorial operation. during design entry, the designer sp ecifies the desired register type; the quartus ii software then selects the mo st efficient register operation for each registered function to optimize resource utilization. the quartus ii software or other synthesis tools can also select the most efficient register operation automatically when synthesizing hdl designs. each programmable register can be clocked by one of two esb-wide clocks. the esb-wide clocks can be ge nerated from device dedicated clock pins, global signals, or local inte rconnect. each clock also has an associated clock enable, generated fr om the local interconnect. the clock and clock enable signals are related for a particular esb; any macrocell using a clock also uses th e associated clock enable. if both the rising and falling edges of a clock are used in an esb, both esb-wide clock signals are used. clock/ enable select product- term select matrix parallel logic expanders (from other macrocells) esb-wide clears esb-wide clock enables esb-wide clocks 32 signals from local interconnect clear select esb output programmable register 222 ena d clrn q
28 altera corporation apex 20k programmable logic device family data sheet the programmable register also suppo rts an asynchronous clear function. within the esb, two asynchronous clears are generated from global signals and the local interconnect. each macrocell can either choose between the two asynchronous clear si gnals or choose to not be cleared. either of the two clear signals ca n be inverted within the esb. figure 15 shows the esb control logic when implementing product-terms. figure 15. esb product-term mode control logic note to figure 15 : (1) apex 20ke devices have four dedicated clocks. parallel expanders parallel expanders are unused product terms that can be allocated to a neighboring macrocell to implemen t fast, complex logic functions. parallel expanders allow up to 32 prod uct terms to feed the macrocell or logic directly, with two product term s provided by the macrocell and 30 parallel expanders provided by the neighboring macrocells in the esb. the quartus ii software compiler can allocate up to 15 sets of up to two parallel expanders per set to the macroc ells automatically. each set of two parallel expanders incurs a smal l, incremental timing delay. figure 16 shows the apex 20k parallel expanders. clk2 clkena2 clk1 clkena1 clr2 clr1 dedicated clocks global signals local interconnect local interconnect local interconnect local interconnect 2 or 4 (1) 4
altera corporation 29 apex 20k programmable logic device family data sheet figure 16. apex 20k parallel expanders embedded system block the esb can implement various type s of memory blocks, including dual-port ram, rom, fifo, and ca m blocks. the esb includes input and output registers; the input re gisters synchronize writes, and the output registers can pipeline designs to improve system performance. the esb offers a dual-port mode, which supports simultaneous reads and writes at two different clock frequencies. figure 17 shows the esb block diagram. figure 17. esb block diagram 32 signals from local interconnect to next macrocell from previous macrocell product- term select matrix product- term select matrix macrocell product- term logi c macrocell product- term logi c parallel expander switch parallel expander switch wraddress[] data[] wren inclock inclocken inaclr rdaddress[] q[] rden outclock outclocken outaclr
30 altera corporation apex 20k programmable logic device family data sheet esbs can implement synchronous ra m, which is easier to use than asynchronous ram. a circuit usin g asynchronous ram must generate the ram write enable ( we ) signal, while ensuring th at its data and address signals meet setup and hold time specifications relative to the we signal. in contrast, the esb?s synchronous ram generates its own we signal and is self-timed with respect to the global clock. circuits using the esb?s self- timed ram must only meet the setup an d hold time specifications of the global clock. esb inputs are driven by the adjacent local interconnect, which in turn can be driven by the megalab or fasttr ack interconnect. because the esb can be driven by the local interconnect, an adjacent le can drive it directly for fast memory access. esb outputs drive the megalab and fasttrack interconnect. in addition , ten esb outputs, nine of which are unique output lines, drive the local interco nnect for fast connection to adjacent les or for fast feedba ck product-term logic. when implementing memory, each esb can be configured in any of the following sizes: 128 16, 256 8, 512 4, 1,024 2, or 2,048 1. by combining multiple esbs, the quartus ii software implements larger memory blocks automatically. for example, two 128 16 ram blocks can be combined to form a 128 32 ram block, and two 512 4 ram blocks can be combined to form a 512 8 ram block. memory performance does not degrade for memory blocks up to 2,048 words deep. each esb can implement a 2,048-word-deep memory; the esbs are used in parallel, eliminating the need for any external control logic and its associated delays. to create a high-speed memory block that is more than 2,048 words deep, esbs drive tri-state lines. each tri-state line connects all esbs in a column of megalab structures, and drives the megalab interconnect and row and column fasttrack in terconnect throughout the column. each esb incorporates a programmable decoder to activate the tri-state driver appropriately. for instance, to impl ement 8,192-word-deep memory, four esbs are used. eleven address lines drive the esb memory, and two more drive the tri-state decoder. depe nding on which 2,048-word memory page is selected, the appropriate es b driver is turned on, driving the output to the tri-state line. the quartus ii software automatically combines esbs with tri-state lines to form deeper memory blocks. the internal tri-state control logic is desi gned to avoid internal contention and floating lines. see figure 18 .
altera corporation 31 apex 20k programmable logic device family data sheet figure 18. deep memory block implemented with multiple esbs the esb implements two forms of du al-port memory: read/write clock mode and input/output clock mode. the esb can also be used for bidirectional, dual-port memory applications in which two ports read or write simultaneously. to implement th is type of dual-port memory, two or four esbs are used to support two simultaneous reads or writes. this functionality is shown in figure 19 . figure 19. apex 20k esb implementing dual-port ram esb esb esb to system logic address decoder port a port b address_a[] address_b[] data_a[] data_b[] we_a we_b clkena_a clkena_b clock a clock b
32 altera corporation apex 20k programmable logic device family data sheet read/write clock mode the read/write clock mode contains two clocks. one clock controls all registers associated with writing: data input, we , and write address. the other clock controls all registers asso ciated with reading: read enable ( re) , read address, and data output. the esb also supports clock enable and asynchronous clear si gnals; these signals also control the read and write registers independently. read/w rite clock mode is commonly used for applications where reads and writes occur at different system frequencies. figure 20 shows the esb in read/write clock mode. figure 20. esb in read/write clock mode note (1) notes to figure 20 : (1) all registers can be cleared asynchrono usly by esb local interconne ct signals, global signals, or the chip-wide reset. (2) apex 20ke devices have four dedicated clocks. dedicated clocks 2 or 4 4 d ena q d ena q d ena q d ena q d ena q data[ ] rdaddress[ ] wraddress[ ] ram/rom 128 16 256 8 512 4 1,024 2 2,048 1 data in read address write address read enable write enable data out outclocken inclocken inclock outclock d ena q write pulse generator rden wren dedicated inputs & global signals to megalab, fasttrack & local interconnect (2)
altera corporation 33 apex 20k programmable logic device family data sheet input/output clock mode the input/output clock mode contains two clocks. one clock controls all registers for inputs into the esb: data input, we , re , read address, and write address. the other clock controls the esb data output registers. the esb also supports clock enable and asynchronous clear signals; these signals also control the reading and writing of register s independently. input/output clock mode is commonly used for applications where the reads and writes occur at the same sy stem frequency, but require different clock enable signals for the input and output registers. figure 21 shows the esb in input/output clock mode. figure 21. esb in input/output clock mode note (1) notes to figure 21 : (1) all registers can be cleared asynchrono usly by esb local interconnect signals, global signals, or the chip-wide reset. (2) apex 20ke devices have four dedicated clocks. single-port mode the apex 20k esb also supports a single-port mode, which is used when simultaneous read s and writes are not required. see figure 22 . dedicated clocks 2 or 4 4 d ena q d ena q d ena q d ena q d ena q data[ ] rdaddress[ ] wraddress[ ] ram/rom 128 16 256 8 512 4 1,024 2 2,048 1 data in read address write address read enable write enable data out outclken inclken inclock outclock d ena q write pulse generator rden wren dedicated inputs & global signals to megalab, fasttrack & local interconnect (2)
34 altera corporation apex 20k programmable logic device family data sheet figure 22. esb in single-port mode note (1) notes to figure 22 : (1) all registers can be asynchronously cl eared by esb local interconne ct signals, global signals, or the chip-wide reset. (2) apex 20ke devices have four dedicated clocks. content-addressable memory in apex 20ke devices, the esb can implement cam. cam can be thought of as the inverse of ram. when read, ram outputs the data for a given address. conversely, cam ou tputs an address for a given data word. for example, if the data fa12 is stored in address 14 , the cam outputs 14 when fa12 is driven into it. cam is used for high-speed search operations. when searching for data within a ram block, the search is performed serially. thus, finding a particular data word can take many cycles. cam searches all addresses in parallel and outputs the address stor ing a particular word. when a match is found, a match flag is set high. figure 23 shows the cam block diagram. dedicated clocks 2 or 4 4 d ena q d ena q d ena q d ena q data[ ] address[ ] ram/rom 128 16 256 8 512 4 1,024 2 2,048 1 data in address write enable data out outclken inclken inclock outclock write pulse generator wren dedicated inputs & global signals to megalab, fasttrack & local interconnect (2)
altera corporation 35 apex 20k programmable logic device family data sheet figure 23. apex 20ke cam block diagram cam can be used in any application requiring high-speed searches, such as networking, communications, data compression, and cache management. the apex 20ke on-chip cam provides faster system performance than traditional discrete cam. integrating cam and logic into the apex 20ke device eliminates off-chip and on-chip delays, improving system performance. when in cam mode, the esb implements 32-word, 32-bit cam. wider or deeper cam can be implemented by combining multiple cams with some ancillary logic implemented in les. the quartus ii software combines esbs and les automatically to create larger cams. cam supports writing ?don?t care? bi ts into words of the memory. the ?don?t-care? bit can be used as a ma sk for cam comparisons; any bit set to ?don?t-care? has no effect on matches. the output of the cam can be encode d or unencoded. when encoded, the esb outputs an encoded address of the data?s location. for instance, if the data is located in address 12 , the esb output is 12 . when unencoded, the esb uses its 16 outputs to show the lo cation of the data over two clock cycles. in this case, if the data is located in address 12 , the 12th output line goes high. when using unencoded outp uts, two clock cycles are required to read the output because a 16-bit outp ut bus is used to show the status of 32 words. the encoded output is better suited for designs that ensure duplicate data is not written into the cam. if duplicate data is wr itten into two locations, the cam?s output will be incorrect. if the cam may contain duplicate data, the unencoded output is a be tter solution; cam with unencoded outputs can distinguish multiple data locations. cam can be pre-loaded with data during configuration, or it can be written during system operation. in most cases, two clock cycles are required to write each word into cam. when ?don?t-care? bits are used, a third clock cycle is required. wraddress[] data[] wren inclock inclocken inaclr data_address[] match outclock outclocken outaclr
36 altera corporation apex 20k programmable logic device family data sheet f for more information on apex 20ke devices and cam, see application note 119 (implementing hi gh-speed search applicat ions with apex cam). driving signals to the esb esbs provide flexible options for driving control signals. different clocks can be used for the esb inputs and outputs. registers can be inserted independently on the data input, data output, read address, write address, we , and re signals. the global signals and the local interconnect can drive the we and re signals. the global sign als, dedicated clock pins, and local interconnect can drive the esb clock signals. because the les drive the local interconnect, the les can control the we and re signals and the esb clock, clock enable, an d asynchronous clear signals. figure 24 shows the esb control signal generation logic. figure 24. esb control signal generation note to figure 24 : (1) apex 20ke devices have four dedicated clocks. an esb is fed by the local interconnect, which is driven by adjacent les (for high-speed connection to the es b) or the megalab interconnect. the esb can drive the local, megalab, or fasttrack interconnect routing structure to drive les and ioes in the same megalab structure or anywhere in the device. rden wren inclock inclkena outclock outclkena dedicated clocks global signals local interconnect local interconnect local interconnect local interconnect 2 or 4 4 local interconnect local interconnect inclr outclr (1)
altera corporation 37 apex 20k programmable logic device family data sheet implementing logic in rom in addition to implementing logi c with product te rms, the esb can implement logic functions when it is programmed with a read-only pattern during configuration, creating a large lut. with luts, combinatorial functions ar e implemented by looking up the results, rather than by computing them. this implementation of combinatorial functions can be faster than using algorithms implemented in general logic, a performance advantage that is further e nhanced by the fast access times of esbs. the large capacity of esbs enables designers to implement complex functions in one logic le vel without the routing delays associated with linked les or distributed ram blocks . parameterized functions such as lpm functions can take advantage of the esb automatically. further, the quartus ii software can implement port ions of a design with esbs where appropriate. programmable spee d/power control apex 20k esbs offer a high-speed mode that supports very fast operation on an esb-by-esb basis. when high sp eed is not required, this feature can be turned off to reduce the esb?s power dissipation by up to 50 % . esbs that run at low power incur a nominal timing delay adder. this turbo bit tm option is available for esbs that implement product-term logic or memory functions. an esb that is not used will be powered down so that it does not consume dc current. designers can program each esb in the apex 20k device for either high-speed or low-power operation. as a result, speed-critical paths in the design can run at high speed, while the remaining paths operate at reduced power. i/o structure the apex 20k ioe contains a bidirectional i/o buffer and a register that can be used either as an input register for external data requiring fast setup times, or as an output register fo r data requiring fast clock-to-output performance. ioes can be used as inpu t, output, or bidi rectional pins. for fast bidirectional i/o ti ming, le registers using local routing can improve setup times and oe timing. the quar tus ii software compiler uses the programmable inversion opti on to invert signals from the row and column interconnect automatically where a ppropriate. because the apex 20k ioe offers one output enable per pin, the quartus ii software compiler can emulate open-drain operation efficiently. the apex 20k ioe includes programmable delays that can be activated to ensure zero hold times, minimum clock-to-output times, input ioe register-to-core register transfers, or core-to-output ioe register transfers. a path in which a pin directly drives a register may require the delay to ensure zero hold time, whereas a path in which a pin drives a register through combinatorial logic may not require the delay.
38 altera corporation apex 20k programmable logic device family data sheet table 10 describes the apex 20k programmable delays and their logic options in the quartus ii software. the quartus ii software compiler can program these delays automatically to minimize setup time while providing a zero hold time. figure 25 shows how fast bidirectional i/os are implemented in apex 20k devices. the register in the apex 20k ioe can be programmed to power-up high or low after configuration is complete. if it is programmed to power-up low, an asynchronous clear can control the register. if it is programmed to power-up high, the register cannot be asynchronously cleared or preset. this feature is useful for cases where the apex 20k device controls an active-low input or another device; it prevents inadvertent activation of the input upon power-up. table 10. apex 20k programmable delay chains programmable delays quartus ii logic option input pin to core delay decrease input delay to internal cells input pin to input register delay dec rease input delay to input register core to output register delay decr ease input delay to output register output register t co delay increase delay to output pin
altera corporation 39 apex 20k programmable logic device family data sheet figure 25. apex 20k bidirectional i/o registers note (1) note to figure 25 : (1) the output enable and input registers are le regi sters in the lab adjacent to the bidirectional pin. vcc oe[7..0] clk[1..0] ena[5..0] clrn[1..0] peripheral control bus clrn d q ena vcc 2 dedicated clock inputs chip-wide output enable clk[3..2] 2 12 vcc vcc chip-wide reset input pin to core delay slew-rate control vccio optional pci clamp output register t delay core to output register delay input pin to input register delay clrn dq ena vcc chip-wide reset input register output register clrn dq ena chip-wide reset vcc oe register vcc 4 dedicated inputs row, column, or local interconnect co open-drain output
40 altera corporation apex 20k programmable logic device family data sheet apex 20ke devices include an enhanced ioe, which drives the fastrow interconnect. the fastrow interco nnect connects a column i/o pin directly to the lab local interconne ct within two megalab structures. this feature provides fast setup time s for pins that drive high fan-outs with complex logic, such as pci design s. for fast bidirectional i/o timing, le registers using local routing can improve setup times and oe timing. the apex 20ke ioe also includes direct support for open-drain operation, giving faster clock-to-ou tput for open-drain signals. some programmable delays in the apex 20ke ioe offer multiple levels of delay to fine-tune setup and hold time re quirements. the quartus ii software compiler can set these delays automatic ally to minimize setup time while providing a zero hold time. table 11 describes the apex 20ke programmable delays and their logic options in the quartus ii software. the register in the apex 20ke ioe can be programmed to power-up high or low after configuration is complete. if it is programmed to power-up low, an asynchronous clear can control the register. if it is programmed to power-up high, an asynchronous preset can control the register. figure 26 shows how fast bidirectional i/o pins are implemented in apex 20ke devices. this feature is useful for cases where the apex 20ke device controls an active-low input or anoth er device; it prevents inadvertent activation of the input upon power-up. table 11. apex 20ke programmable delay chains programmable delays quartus ii logic option input pin to core delay decrease input delay to internal cells input pin to input register delay decrease input delay to input registers core to output register delay dec rease input delay to output register output register t co delay increase delay to output pin clock enable delay increase clock enable delay
altera corporation 41 apex 20k programmable logic device family data sheet figure 26. apex 20ke bidi rectional i/o registers notes (1) , (2) notes to figure 26 : (1) this programmable delay has four settings: off and three levels of delay. (2) the output enable and input re gisters are le registers in the lab adjacent to the bidirectional pin. vcc oe[7..0] clk[1..0] ena[5..0] clrn[1..0] peripheral control bus clrn/ prn d q ena vcc 4 dedicated clock inputs chip-wide output enable clk[3..0] 4 12 vcc vcc chip-wide reset input pin to core delay (1) slew-rate control open-drain output vccio optional pci clamp output register t delay core to output register delay input pin to input register delay clrn dq ena vcc chip-wide reset input register output register clrn dq ena chip-wide reset vcc oe register vcc 4 dedicated inputs row, column, fastrow, or local interconnect clock enable delay (1 ) input pin to core delay (1) co input pin to core delay (1)
42 altera corporation apex 20k programmable logic device family data sheet each ioe drives a row, column, megalab, or local interconnect when used as an input or bidirectional pin. a row ioe can drive a local, megalab, row, and column interconnect; a column ioe can drive the column interconnect. figure 27 shows how a row ioe connects to the interconnect. figure 27. row ioe connection to the interconnect row in terc onn ect m e g a lab in terc onn ect any le ca n dr iv e a pin t h r ough t h e r ow, c olumn, a n d m e g a lab in terc onn ect . an le ca n dr iv e a pin t h r ough t h e lo ca l in terc onn ect fo r f aster c lo c k- t o-ou t pu t t im es . ioe ioe e ac h ioe ca n dr iv e lo ca l, m e g a lab, r ow, a n d c olumn in terc onn ect . e ac h ioe data a n d oe s ign a l i s dr iv e n by t h e lo ca l in terc onn ect . lab
altera corporation 43 apex 20k programmable logic device family data sheet figure 28 shows how a column ioe connects to the interconnect. figure 28. column ioe connection to the interconnect dedicated fast i/o pins apex 20ke devices incorporate an e nhancement to suppo rt bidirectional pins with high internal fanout such as pci control signals. these pins are called dedicated fast i/o pins ( fast1 , fast2 , fast3 , and fast4 ) and replace dedicated inputs. these pins can be used for fast clock, clear, or high fanout logic signal distribution. they also can drive out. the dedicated fast i/o pin data output and tri-state control are driven by local interconnect from the adjacent megalab for high speed. row in terc onn ect column in terc onn ec t e ac h ioe ca n dr iv e c olumn in terc onn ect . in apex 2 0ke de vi ces , ioe s ca n a l s o dr iv e f ast row in terc onn ect . e ac h ioe data a n d oe s ign a l i s dr iv e n by lo ca l in terc onn ect . any le o r esb ca n dr iv e a c olumn pin t h r ough a r ow, c olumn, a n d m e g a lab in terc onn ect . ioe ioe lab an le o r esb ca n dr iv e a pin t h r ough a lo ca l in terc onn ect fo r f aster c lo c k- t o-ou t pu t t im es . m e g a lab in terc onn ect
44 altera corporation apex 20k programmable logic device family data sheet advanced i/o standard support apex 20ke ioes support the following i/o standards: lvttl, lvcmos, 1.8-v i/o, 2.5-v i/o, 3.3- v pci, pci-x, 3.3-v agp, lvds, lvpecl, gtl+, ctt, hstl class i, sstl-3 class i and ii, and sstl-2 class i and ii. f for more information on i/o standards supported by apex 20ke devices, see application note 117 (u sing selectable i/o standards in altera devices) . the apex 20ke device contains eight i/o banks. in qfp packages, the banks are linked to form four i/o ba nks. the i/o banks directly support all standards except lvds and lvpecl. all i/o banks can support lvds and lvpecl with the additi on of external resistors. in addition, one block within a bank contains circuitry to support hi gh-speed true-lvds and lvpecl inputs, and anoth er block within a particular bank supports high-speed true-lvds and lvpecl ou tputs. the lvds blocks support all of the i/o standards. each i/o bank has its own vccio pins. a single device can support 1.8-v, 2.5-v, an d 3.3-v interfaces; each bank can support a different standard independ ently. each bank can also use a separate v ref level so that each bank can support any of the terminated standards (such as sstl-3) independen tly. within a bank, any one of the terminated standards can be supported. ep20k300e and larger apex 20ke devices support the lvds interface for data pins (smaller devices support lvds clock pins, but not data pins). all ep20k300e and larger devices support the lvds interface for data pins up to 155 mbit per channel; EP20K400E devices and larger with an x-suffix on the ordering code add a serializer/deserializer circuit and pll for higher-speed support. each bank can support multiple standards with the same vccio for output pins. each bank can support one voltage-referenced i/o standard, but it can support multiple i /o standards with the same vccio voltage level. for example, when vccio is 3.3 v, a bank can support lvttl, lvcmos, 3.3-v pci, and sstl-3 for inputs and outputs. when the lvds banks are not used as lvds i/o banks, they support all of the other i/o standards. figure 29 shows the arrangement of the apex 20ke i/o banks.
altera corporation 45 apex 20k programmable logic device family data sheet figure 29. apex 20ke i/o banks notes to figure 29 : (1) for more information on placing i/ o pins in lvds blocks, refer to the guidelines for using lvds blocks section in application note 120 (using lvds in apex 20ke devices ). (2) if the lvds input and output blocks are not used for lvds, they can support all of the i/o standards and can be used as inpu t, output, or bidirectional pins with v ccio set to 3.3 v, 2.5 v, or 1.8 v. power sequencing & hot socketing because apex 20k and apex 20ke de vices can be used in a mixed- voltage environment, they have been designed specifically to tolerate any possible power-up sequence. therefore, the v ccio and v ccint power supplies may be powered in any order. f for more information, please refer to the ?power sequencing considerations? section in the configuring apex 20ke & apex 20kc devices chapter of the configuration devices handbook . signals can be driven into apex 20k devices before and during power-up without damaging the device. in addi tion, apex 20k devices do not drive out during power-up. once operatin g conditions are reached and the device is configured, apex 20k an d apex 20ke devices operate as specified by the user. lvds/lvpec l inpu t blo c k ( 2 ) (1) lvds/lvpecl ou t pu t blo c k ( 2 ) (1) r e gul ar i/o blo c k s suppo rt lvttl lvcmos 2 .5 v 1.8 v 3.3 v pci lvpecl hstl cl ass i gtl+ sstl- 2 cl ass i a n d ii sstl-3 cl ass i a n d ii ctt agp in d ivi d u a l pow er bu s i/o b a nk 8 i/o b a nk 1 i/o b a nk 2 i/o b a nk 3 i/o b a nk 4 i/o b a nk 5 i/o b a nk 6 i/o b a nk 7
46 altera corporation apex 20k programmable logic device family data sheet under hot socketing conditions, apex 20ke devices will not sustain any damage, but the i/o pins will drive out. multivolt i/o interface the apex device architecture su pports the multivolt i/o interface feature, which allows apex devices in all packages to interface with systems of different supply voltag es. the devices have one set of vcc pins for internal operation and input buffers ( vccint ), and another set for i/o output drivers ( vccio ). the apex 20k vccint pins must always be connected to a 2.5 v power supply. with a 2.5-v v ccint level, input pins are 2.5-v, 3.3-v, and 5.0-v tolerant. the vccio pins can be connected to either a 2.5-v or 3.3-v power supply, depending on the ou tput requirements. when vccio pins are connected to a 2.5-v power supply, the output levels are compatible with 2.5-v systems. when the vccio pins are connected to a 3.3-v power supply, the output high is 3.3 v and is compatible with 3.3-v or 5.0-v systems. table 12 summarizes 5.0-v tolerant ap ex 20k multivolt i/o support. notes to table 12 : (1) the pci clamping diode mus t be disabled to drive an input with voltages higher than v ccio . (2) when v ccio = 3.3 v, an apex 20k device ca n drive a 2.5-v device with 3.3-v tolerant inputs. open-drain output pins on 5.0-v tolerant apex 20k devices (with a pull- up resistor to the 5.0-v supply) ca n drive 5.0-v cmos input pins that require a v ih of 3.5 v. when the pin is inacti ve, the trace will be pulled up to 5.0 v by the resistor. the open-drain pin will only drive low or tri-state; it will never drive high. the rise time is dependent on the value of the pull- up resistor and load impedance. the i ol current specification should be considered when selecting a pull-up resistor. table 12. 5.0-v tolerant apex 20k multivolt i/o support v ccio (v) input signals (v) output signals (v) 2.5 3.3 5.0 2.5 3.3 5.0 2.5 vv (1) v (1) v 3.3 vv v (1) v (2) vv
altera corporation 47 apex 20k programmable logic device family data sheet apex 20ke devices also support the mu ltivolt i/o interface feature. the apex 20ke vccint pins must always be connected to a 1.8-v power supply. with a 1.8-v v ccint level, input pins are 1.8-v, 2.5-v, and 3.3-v tolerant. the vccio pins can be connected to either a 1.8-v, 2.5-v, or 3.3-v power supply, depending on the i/o standard requirements. when the vccio pins are connected to a 1.8-v powe r supply, the output levels are compatible with 1.8-v systems. when vccio pins are connected to a 2.5-v power supply, the output levels are co mpatible with 2.5-v systems. when vccio pins are connected to a 3.3-v po wer supply, the output high is 3.3 v and compatible with 3.3-v or 5. 0-v systems. an apex 20ke device is 5.0-v tolerant with th e addition of a resistor. table 13 summarizes apex 20ke multivolt i/o support. notes to table 13 : (1) the pci clamping diode must be disabled to drive an input with voltages higher than v ccio , except for the 5.0-v input case. (2) an apex 20ke device can be made 5.0-v tolerant with th e addition of an external resistor. you also need a pci clamp and series resistor. (3) when v ccio = 3.3 v, an apex 20ke device can drive a 2.5-v device with 3.3-v tolerant inputs. clocklock & clockboost features apex 20k devices support the cl ocklock and cl ockboost clock management features, which are impl emented with plls. the clocklock circuitry uses a synchronizing pll that reduces the clock delay and skew within a device. this reduction mi nimizes clock-to-output and setup times while maintaining zero hold time s. the clockboost circuitry, which provides a clock multiplier, allows the designer to enhance device area efficiency by sharing resources within the device. the clockboost circuitry allows the desi gner to distribute a low-speed clock and multiply that clock on-device. apex 20k device s include a high-speed clock tree; unlike asics, the user does not have to design and optimize the clock tree. the clocklock and clockboost features work in conjunction with the apex 20k device?s high-speed clock to provide significant improvements in system performance and band-width . devices with an x-suffix on the ordering code include the clocklock circuit. the clocklock and clockb oost features in apex 20k devices are enabled through the quartus ii software. extern al devices are not required to use these features. table 13. apex 20ke multivolt i/o support note (1) v ccio (v) input signals (v) output signals (v) 1.8 2.5 3.3 5.0 1.8 2.5 3.3 5.0 1.8 vv v v 2.5 vvv v 3.3 vvv (2) v (3)
48 altera corporation apex 20k programmable logic device family data sheet for designs that require both a multiplied and non-multiplied clock, the clock trace on the board can be connected to clk2p . table 14 shows the combinations supported by the clockl ock and clockboost circuitry. the clk2p pin can feed both the clocklock and clockboost circuitry in the apex 20k device. however, when both circuits are used, the other clock pin ( clk1p ) cannot be used. apex 20ke clocklock feature apex 20ke devices include an enhanc ed clocklock feature set. these devices include up to four plls, which can be used independently. two plls are designed for either general- purpose use or lvds use (on devices that support lvds i/o pins). the re maining two plls are designed for general-purpose use. the ep20k200e an d smaller devices have two plls; the ep20k300e and larger de vices have four plls. the following sections describe some of the features offered by the apex 20ke plls. external pll feedback the clocklock circ uit?s output can be driven off-chip to clock other devices in the system; further, the feed back loop of the pll can be routed off-chip. this feature allows the design er to exercise fine control over the i/o interface between the apex 20ke device and another high-speed device, such as sdram. clock multiplication the apex 20ke clockboost circuit can multiply or divide clocks by a programmable number. the clock can be multiplied by m /( n k ) or m /( n v ), where m and k range from 2 to 160, and n and v range from 1 to 16. clock multiplication and divisi on can be used for time-domain multiplexing and other functions, which can reduce design le requirements. table 14. multiplication factor combinations clock 1 clock 2 1 1 1 , 2 2 1 , 2 , 4 4
altera corporation 49 apex 20k programmable logic device family data sheet clock phase & delay adjustment the apex 20ke clockshift feature allo ws the clock phase and delay to be adjusted. the clock phase can be adju sted by 90 steps. the clock delay can be adjusted to increase or decrease the clock delay by an arbitrary amount, up to one clock period. lvds support two plls are designed to support the lvds interface. when using lvds, the i/o clock runs at a slower rate th an the data transfer rate. thus, plls are used to multiply the i/o clock inte rnally to capture the lvds data. for example, an i/o clock may run at 105 mhz to support 840 megabits per second (mbps) lvds data transfer. in this example, the pll multiplies the incoming clock by eight to support th e high-speed data transfer. you can use plls in EP20K400E and larger devices for high-speed lvds interfacing. lock signals the apex 20ke clocklock circuitry supports individual lock signals. the lock signal drives high when the clocklock circuit has locked onto the input clock. the lock signals are optional for each clocklock circuit; when not used, they are i/o pins. clocklock & clockboost timing parameters for the clocklock and clockboost ci rcuitry to functi on properly, the incoming clock must meet certain requ irements. if these specifications are not met, the circuitry may not lock onto the incoming clock, which generates an erroneous clock within the device. the clock generated by the clocklock an d clockboost circ uitry must also meet certain specifications. if the incoming cloc k meets these requ irements during configuration, the apex 20k cloc klock and cl ockboost circ uitry will lock onto the clock during configuration. the circuit will be ready for use immediately after configuration. in apex 20ke devices, the clock input standard is programmable, so the pl l cannot respond to the clock until the device is configured. the pll lo cks onto the input cl ock as soon as configuration is complete. figure 30 shows the incoming and generated clock specifications. 1 for more information on clockl ock and clockboos t circuitry, see application note 115: using the clocklock and clockboost pll features in apex devices .
50 altera corporation apex 20k programmable logic device family data sheet figure 30. specificat ions for the incoming & generated clocks note (1) note to figure 30 : (1) the ti parameter refers to the nominal input clock period; the to parameter refers to the nominal output clock period. table 15 summarizes the apex 20k clocklock an d clockboost parameters for -1 speed-grade devices. input clock clocklock generated clock f clk1 f clk2 f clk4 t induty t i + t clkdev t r t f t o t i + t inclkstb t o t o t jitter t o + t jitter t outduty ,, table 15. apex 20k clocklock & cl ockboost parameters for -1 speed-grade devices (part 1 of 2) symbol parameter min max unit f out output frequency 25 180 mhz f clk1 (1) input clock frequency (clockboost clock multiplication factor equals 1) 25 180 (1) mhz f clk2 input clock frequency (clockboost clock multiplication factor equals 2) 16 90 mhz f clk4 input clock frequency (clockboost clock multiplication factor equals 4) 10 48 mhz t outduty duty cycle for clockl ock/clockboost-generated clock 40 60 % f clkdev input deviation from user specification in the quartus ii software (clockboost clock multiplication factor equals 1) (2) 25,000 (3) ppm t r input rise time 5 ns t f input fall time 5 ns t lock time required for cloc klock/clockboost to acquire lock (4) 10 s
altera corporation 51 apex 20k programmable logic device family data sheet notes to table 15 : (1) the pll input frequency range for the ep20k100-1 x device for 1x multiplication is 25 mhz to 175 mhz. (2) all input clock specifications must be met. the pll may not lock onto an incoming clock if the clock specifications are not met, creating an erro neous clock within the device. (3) during device configuration, the clocklock and clockboost circuitry is configured firs t. if the incoming clock is supplied during configuration, the clocklock and clockboos t circuitry locks during configuration, because the lock time is less than the configuration time. (4) the jitter specification is me asured under long-term observation. (5) if the input clock stability is 100 ps, t jitter is 250 ps. table 16 summarizes the apex 20k clocklock an d clockboost parameters for -2 speed grade devices. t skew skew delay between related clocklock/clockb oost-generated clocks 500 ps t jitter jitter on clocklock/cl ockboost-generated clock (5) 200 ps t inclkstb input clock stability (measured between adjacent clocks) 50 ps table 15. apex 20k clocklock & cl ockboost parameters for -1 speed-grade devices (part 2 of 2) symbol parameter min max unit table 16. apex 20k clocklock & clockboost parameters for -2 speed grade devices symbol parameter min max unit f out output frequency 25 170 mhz f clk1 input clock frequency (clockboost clock multiplication factor equals 1) 25 170 mhz f clk2 input clock frequency (clockboost clock multiplication factor equals 2) 16 80 mhz f clk4 input clock frequency (clockboost clock multiplication factor equals 4) 10 34 mhz t outduty duty cycle for clocklock/clockboost-generated clock 40 60 % f clkdev input deviation from user specification in the quartus ii software (clockboost clock multiplication factor equals one) (1) 25,000 (2) ppm t r input rise time 5ns t f input fall time 5ns t lock time required for clocklock/ clockboost to acquire lock (3) 10 s t skew skew delay between related clocklock/ clockboost- generated clock 500 500 ps t jitter jitter on clocklock/ clo ckboost-generated clock (4) 200 ps t inclkstb input clock stability (measured between adjacent clocks) 50 ps
52 altera corporation apex 20k programmable logic device family data sheet notes to table 16 : (1) to implement the clocklock and cloc kboost circuitry with the quartus ii so ftware, designers must specify the input frequency. the quartus ii software tunes the pll in the clocklock and clockboost circuitry to this frequency. the f clkdev parameter specifies how much th e incoming clock can differ from the specified frequency during device operation. simulation do es not reflect this parameter. (2) twenty-five thousand parts per million (ppm) equates to 2.5 % of input clock period. (3) during device configuration, the clocklock and clockboost c ircuitry is configured before the rest of the device. if the incoming clock is supplied during configuration, the clocklock and clockboost circuitry locks during configuration because the t lock value is less than the time required for configuration. (4) the t jitter specification is measured under long-term observation. tables 17 and 18 summarize the clocklock and clockboost parameters for apex 20ke devices. table 17. apex 20ke clocklock & clockboost parameters note (1) symbol parameter conditions min typ max unit t r input rise time 5ns t f input fall time 5ns t induty input duty cycle 40 60 % t injitter input jitter peak-to-peak 2 % of input period peak-to- peak t outjitter jitter on clocklock or clockboost- generated clock 0.35 % of output period rms t outduty duty cycle for clocklock or clockboost-generated clock 45 55 % t lock (2) , (3) time required for clocklock or clockboost to acquire lock 40 s
altera corporation 53 apex 20k programmable logic device family data sheet table 18. apex 20ke clock input & ou tput parameters (part 1 of 2) note (1) symbol parameter i/o standard -1x speed grade -2x speed grade units min max min max f vco (4) voltage controlled oscillator operating range 200 500 200 500 mhz f clock0 clock0 pll output frequency for internal use 1.5 335 1.5 200 mhz f clock1 clock1 pll output frequency for internal use 20 335 20 200 mhz f clock0_ext output clock frequency for external clock0 output 3.3-v lvttl 1.5 245 1.5 226 mhz 2.5-v lvttl 1.5 234 1.5 221 mhz 1.8-v lvttl 1.5 223 1.5 216 mhz gtl+ 1.5 205 1.5 193 mhz sstl-2 class i 1.5 158 1.5 157 mhz sstl-2 class ii 1.5 142 1.5 142 mhz sstl-3 class i 1.5 166 1.5 162 mhz sstl-3 class ii 1.5 149 1.5 146 mhz lvds 1.5 420 1.5 350 mhz f clock1_ext output clock frequency for external clock1 output 3.3-v lvttl 20 245 20 226 mhz 2.5-v lvttl 20 234 20 221 mhz 1.8-v lvttl 20 223 20 216 mhz gtl+ 20 205 20 193 mhz sstl-2 class i 20 158 20 157 mhz sstl-2 class ii 20 142 20 142 mhz sstl-3 class i 20 166 20 162 mhz sstl-3 class ii 20 149 20 146 mhz lvds 20 420 20 350 mhz
54 altera corporation apex 20k programmable logic device family data sheet notes to tables 17 and 18 : (1) all input clock specifications must be met. the pll may not lock onto an incoming clock if the clock specifications are not met, creating an erro neous clock within the device. (2) the maximum lock time is 40 s or 2000 input clock cycles, whichever occurs first. (3) before configuration, the pll circuits are disable and powered down. during configur ation, the plls are still disabled. the plls begin to lock once the device is in the user mode. if the clock enable feature is used, lock begins once the clklk_ena pin goes high in user mode. (4) the pll vco operating range is 200 mhz e f vco e 840 mhz for lvds mode. signaltap embedded logic analyzer apex 20k devices include device enha ncements to support the signaltap embedded logic analyzer. by includ ing this circuitry, the apex 20k device provides the ability to monitor design operation over a period of time through the ieee st d. 1149.1 (jtag) circuitry; a designer can analyze internal logic at speed without bringi ng internal signal s to the i/o pins. this feature is particularly import ant for advanced packages such as fineline bga packages because adding a connection to a pin during the debugging process can be difficult after a board is designed and manufactured. f in input clock frequency 3.3-v lvttl 1.5 290 1.5 257 mhz 2.5-v lvttl 1.5 281 1.5 250 mhz 1.8-v lvttl 1.5 272 1.5 243 mhz gtl+ 1.5 303 1.5 261 mhz sstl-2 class i 1.5 291 1.5 253 mhz sstl-2 class ii 1.5 291 1.5 253 mhz sstl-3 class i 1.5 300 1.5 260 mhz sstl-3 class ii 1.5 300 1.5 260 mhz lvds 1.5 420 1.5 350 mhz table 18. apex 20ke clock input & ou tput parameters (part 2 of 2) note (1) symbol parameter i/o standard -1x speed grade -2x speed grade units min max min max
altera corporation 55 apex 20k programmable logic device family data sheet ieee std. 1149.1 (jtag) boundary-scan support all apex 20k devices provide jtag bst circuitry that complies with the ieee std. 1149.1-1990 specification. jtag boundary-scan testing can be performed before or after configurat ion, but not during configuration. apex 20k devices can also use the jtag port for configuration with the quartus ii software or with hard ware using either jam files ( .jam ) or jam byte-code files ( .jbc ). finally, apex 20k device s use the jtag port to monitor the logic operation of the de vice with the signaltap embedded logic analyzer. apex 20k devices support the jtag instructions shown in table 19 . although ep20k1500e devices su pport the jtag bypass and signaltap instructions, th ey do not support boundary-scan testing or the use of the jtag port for configuration. note to table 19 : (1) the ep20k1500e device supports the jtag bypass instruction and the signaltap instructions. table 19. apex 20k jtag instructions jtag instruction description sample/preload allows a snapshot of signals at t he device pins to be c aptured and examined during normal device operation, and permits an initial data pattern to be output at the device pins. also used by the signaltap embedded logic analyzer. extest allows the external circ uitry and board-level interconnections to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. bypass (1) places the 1-bit bypas s register between the tdi and tdo pins, which allows the bst data to pass synchronously through sele cted devices to adjac ent devices during normal device operation. usercode selects the 32-bit usercode register and places it between the tdi and tdo pins, allowing the usercode to be serially shifted out of tdo . idcode selects the idcode r egister and places it between tdi and tdo , allowing the idcode to be serially shifted out of tdo . icr instructions used when configuring an apex 20k dev ice via the jtag port with a masterblaster tm or byteblastermv tm download cable, or when using a jam file or jam byte-code file via an embedded processor. signaltap instructions (1) monitors internal device operation with the signaltap embedded logic analyzer.
56 altera corporation apex 20k programmable logic device family data sheet the apex 20k device instruction register length is 10 bits. the apex 20k device usercode register length is 32 bits. tables 20 and 21 show the boundary-scan register length and device idcode information for apex 20k devices. note to table 20 : (1) this device does not support jtag boundary scan testing. table 20. apex 20k boundary-scan register length device boundary-scan register length ep20k30e 420 ep20k60e 624 ep20k100 786 ep20k100e 774 ep20k160e 984 ep20k200 1,176 ep20k200e 1,164 ep20k300e 1,266 ep20k400 1,536 EP20K400E 1,506 ep20k600e 1,806 ep20k1000e 2,190 ep20k1500e 1 (1)
altera corporation 57 apex 20k programmable logic device family data sheet notes to table 21 : (1) the most significant bit (msb) is on the left. (2) the idcode?s least significant bit (lsb) is always 1. figure 31 shows the timing requirem ents for the jtag signals. figure 31. apex 20k jtag waveforms table 21. 32-bit apex 20k device idcode device idcode (32 bits) (1) version (4 bits) part number (16 bits) manufacturer identity (11 bits) 1 (1 bit) (2) ep20k30e 0000 1000 0000 0011 0000 000 0110 1110 1 ep20k60e 0000 1000 0000 0110 0000 000 0110 1110 1 ep20k100 0000 0000 0100 0001 0110 000 0110 1110 1 ep20k100e 0000 1000 0001 0000 0000 000 0110 1110 1 ep20k160e 0000 1000 0001 0110 0000 000 0110 1110 1 ep20k200 0000 0000 1000 0011 0010 000 0110 1110 1 ep20k200e 0000 1000 0010 0000 0000 000 0110 1110 1 ep20k300e 0000 1000 0011 0000 0000 000 0110 1110 1 ep20k400 0000 0001 0110 0110 0100 000 0110 1110 1 EP20K400E 0000 1000 0100 0000 0000 000 0110 1110 1 ep20k600e 0000 1000 0110 0000 0000 000 0110 1110 1 ep20k1000e 0000 1001 0000 0000 0000 000 0110 1110 1 tdo tck t jpzx t jpco t jph t jpxz t jcp t jpsu t jcl t jch tdi tms signal to be captured signal to be driven t jszx t jssu t jsh t jsco t jsxz
58 altera corporation apex 20k programmable logic device family data sheet table 22 shows the jtag timing parameters and values for apex 20k devices. f for more information, se e the following documents: application note 39 (ieee std. 1149.1 (jtag) boundary-scan testing in altera devices) jam programming & test language specification generic testing each apex 20k device is functionally tested. complete testing of each configurable static random access memory (sram) bit and all logic functionality ensures 100 % yield. ac test measurements for apex 20k devices are made under conditions equivalent to those shown in figure 32 . multiple test patterns can be used to configure devices during all stages of the production flow. table 22. apex 20k jtag timing parameters & values symbol parameter min max unit t jcp tck clock period 100 ns t jch tck clock high time 50 ns t jcl tck clock low time 50 ns t jpsu jtag port setup time 20 ns t jph jtag port hold time 45 ns t jpco jtag port clock to output 25 ns t jpzx jtag port high impedance to valid output 25 ns t jpxz jtag port valid output to high impedance 25 ns t jssu capture register setup time 20 ns t jsh capture register hold time 45 ns t jsco update register clock to output 35 ns t jszx update register high impedance to valid output 35 ns t jsxz update register valid output to high impedance 35 ns
altera corporation 59 apex 20k programmable logic device family data sheet figure 32. apex 20k ac test conditions note (1) note to figure 32 : (1) power supply transients can affect ac measurements. simultane ous transitions of multiple outputs should be avoided for accurate measurement. threshold tests must not be performed under ac cond itions. large-amplitude, fast-ground- current transients normally occur as the device outputs discharge the load capacitances. when these transients flow through the parasitic inductance between the device ground pin and the test syst em ground, significant reductions in observable noise immunity can result. operating conditions tables 23 through 26 provide information on absolute maximum ratings, recommended operating conditions , dc operating conditions, and capacitance for 2.5-v apex 20k devices. system c1 (includes jig capacitance) device input rise and fall times < 3 ns device output to test table 23. apex 20k 5.0-v tolerant de vice absolute maximum ratings notes (1) , (2) symbol parameter conditions min max unit v ccint supply voltage with respect to ground (3) ?0.5 3.6 v v ccio ?0.5 4.6 v v i dc input voltage ?2.0 5.75 v i out dc output current, per pin ?25 25 ma t stg storage temperature no bias ?65 150 c t amb ambient temperature under bias ?65 135 c t j junction temperature pqfp, rqfp, tqfp, and bga packages, under bias 135 c ceramic pga packages, under bias 150 c
60 altera corporation apex 20k programmable logic device family data sheet table 24. apex 20k 5.0-v tolerant de vice recommended operating conditions note (2) symbol parameter conditions min max unit v ccint supply voltage for internal logic and input buffers (4) , (5) 2.375 (2.375) 2.625 (2.625) v v ccio supply voltage for output buffers, 3.3-v operation (4) , (5) 3.00 (3.00) 3.60 (3.60) v supply voltage for output buffers, 2.5-v operation (4) , (5) 2.375 (2.375) 2.625 (2.625) v v i input voltage (3) , (6) ?0.5 5.75 v v o output voltage 0v ccio v t j junction temperature for commercial use 0 85 c for industrial use ?40 100 c t r input rise time 40 ns t f input fall time 40 ns table 25. apex 20k 5.0-v tolerant device dc operating conditions (part 1 of 2) notes (2) , (7) , (8) symbol parameter conditions min typ max unit v ih high-level input voltage 1.7, 0.5 v ccio (9) 5.75 v v il low-level input voltage ?0.5 0.8, 0.3 v ccio (9) v v oh 3.3-v high-level ttl output voltage i oh = ?8 ma dc, v ccio =3.00 v (10) 2.4 v 3.3-v high-level cmos output voltage i oh = ?0.1 ma dc, v ccio =3.00 v (10) v ccio ?0.2 v 3.3-v high-level pci output voltage i oh = ?0.5 ma dc, v ccio = 3.00 to 3.60 v (10) 0.9 v ccio v 2.5-v high-level output voltage i oh = ?0.1 ma dc, v ccio =2.30 v (10) 2.1 v i oh = ?1 ma dc, v ccio =2.30 v (10) 2.0 v i oh = ?2 ma dc, v ccio =2.30 v (10) 1.7 v
altera corporation 61 apex 20k programmable logic device family data sheet v ol 3.3-v low-level ttl output voltage i ol = 12 ma dc, v ccio =3.00 v (11) 0.45 v 3.3-v low-level cmos output voltage i ol = 0.1 ma dc, v ccio =3.00 v (11) 0.2 v 3.3-v low-level pci output voltage i ol = 1.5 ma dc, v ccio = 3.00 to 3.60 v (11) 0.1 v ccio v 2.5-v low-level output voltage i ol = 0.1 ma dc, v ccio =2.30 v (11) 0.2 v i ol = 1 ma dc, v ccio =2.30 v (11) 0.4 v i ol = 2 ma dc, v ccio =2.30 v (11) 0.7 v i i input pin leakage current v i = 5.75 to ?0.5 v ?10 10 a i oz tri-stated i/o pin leakage current v o = 5.75 to ?0.5 v ?10 10 a i cc0 v cc supply current (standby) (all esbs in power-down mode) v i = ground, no load, no toggling inputs, -1 speed grade (12) 10 ma v i = ground, no load, no toggling inputs, -2, -3 speed grades (12) 5ma r conf value of i/o pin pull-up resistor before and during configuration v ccio = 3.0 v (13) 20 50 w v ccio = 2.375 v (13) 30 80 w table 25. apex 20k 5.0-v tolerant device dc operating conditions (part 2 of 2) notes (2) , (7) , (8) symbol parameter conditions min typ max unit
62 altera corporation apex 20k programmable logic device family data sheet notes to tables 23 through 26 : (1) see the operating requirements for altera devices data sheet . (2) all apex 20k devices are 5.0-v tolerant. (3) minimum dc input is ?0.5 v. during transitions, the inpu ts may undershoot to ?2.0 v or overshoot to 5.75 v for input currents less than 100 ma and periods shorter than 20 ns. (4) numbers in parentheses are for in dustrial-temperatur e-range devices. (5) maximum v cc rise time is 100 ms, and v cc must rise monotonically. (6) all pins, including dedicated inputs, clock i/o, and jtag pins, may be driven before v ccint and v ccio are powered. (7) typical values are for t a = 25 c, v ccint = 2.5 v, and v ccio = 2.5 or 3.3 v. (8) these values are specified in the apex 20k device recommended operating conditions, shown in table 26 on page 62. (9) the apex 20k input buffers are compatible with 2.5-v and 3.3-v (lvttl and lvcmos) signals. additionally, the input buffers are 3.3-v pci compliant when v ccio and v ccint meet the relationship shown in figure 33 on page 68. (10) the i oh parameter refers to high-level ttl, pci or cmos output current. (11) the i ol parameter refers to low-level ttl, pci, or cmos outp ut current. this parameter applies to open-drain pins as well as output pins. (12) this value is specified for normal device operation. the value may vary during power-up. (13) pin pull-up resistance values will be lower if an external source drives the pin higher than v ccio . (14) capacitance is sample-tested only. tables 27 through 30 provide information on absolute maximum ratings, recommended operating conditions, dc operating conditions, and capacitance for 1.8-v apex 20ke devices. table 26. apex 20k 5.0-v tolerant device capacitance notes (2) , (14) symbol parameter conditions min max unit c in input capacitance v in = 0 v, f = 1.0 mhz 8 pf c inclk input capacitance on dedicated clock pin v in = 0 v, f = 1.0 mhz 12 pf c out output capacitance v out = 0 v, f = 1.0 mhz 8 pf table 27. apex 20ke device absolute maximum ratings note (1) symbol parameter conditions min max unit v ccint supply voltage with respect to ground (2) ?0.5 2.5 v v ccio ?0.5 4.6 v v i dc input voltage ?0.5 4.6 v i out dc output current, per pin ?25 25 ma t stg storage temperature no bias ?65 150 c t amb ambient temperature under bias ?65 135 c t j junction temperature pqfp, rqfp, tqfp, and bga packages, under bias 135 c ceramic pga packages, under bias 150 c
altera corporation 63 apex 20k programmable logic device family data sheet table 28. apex 20ke device reco mmended operating conditions symbol parameter conditions min max unit v ccint supply voltage for internal logic and input buffers (3) , (4) 1.71 (1.71) 1.89 (1.89) v v ccio supply voltage for output buffers, 3.3-v operation (3) , (4) 3.00 (3.00) 3.60 (3.60) v supply voltage for output buffers, 2.5-v operation (3) , (4) 2.375 (2.375) 2.625 (2.625) v supply voltage for output buffers, 1.8-v operation (3) , (4) 1.71 (1.71) 1.89 (1.89) v v i input voltage (5) , (6) ?0.5 4.0 v v o output voltage 0v ccio v t j junction temperature for commercial use 0 85 c for industrial use ?40 100 c t r input rise time 40 ns t f input fall time 40 ns
64 altera corporation apex 20k programmable logic device family data sheet table 29. apex 20ke device dc operating conditions notes (7) , (8) , (9) symbol parameter conditions min typ max unit v ih high-level lvttl, cmos, or 3.3-v pci input voltage 1.7, 0.5 v ccio (10) 4.1 v v il low-level lvttl, cmos, or 3.3-v pci input voltage ?0.5 0.8, 0.3 v ccio (10) v v oh 3.3-v high-level lvttl output voltage i oh = ?12 ma dc, v ccio =3.00 v (11) 2.4 v 3.3-v high-level lvcmos output voltage i oh = ?0.1 ma dc, v ccio =3.00 v (11) v ccio ?0.2 v 3.3-v high-level pci output voltage i oh = ?0.5 ma dc, v ccio = 3.00 to 3.60 v (11) 0.9 v ccio v 2.5-v high-level output voltage i oh = ?0.1 ma dc, v ccio =2.30 v (11) 2.1 v i oh = ?1 ma dc, v ccio =2.30 v (11) 2.0 v i oh = ?2 ma dc, v ccio =2.30 v (11) 1.7 v v ol 3.3-v low-level lvttl output voltage i ol = 12 ma dc, v ccio =3.00 v (12) 0.4 v 3.3-v low-level lvcmos output voltage i ol = 0.1 ma dc, v ccio =3.00 v (12) 0.2 v 3.3-v low-level pci output voltage i ol = 1.5 ma dc, v ccio = 3.00 to 3.60 v (12) 0.1 v ccio v 2.5-v low-level output voltage i ol = 0.1 ma dc, v ccio =2.30 v (12) 0.2 v i ol = 1 ma dc, v ccio =2.30 v (12) 0.4 v i ol = 2 ma dc, v ccio =2.30 v (12) 0.7 v i i input pin leakage current v i = 4.1 to ?0.5 v (13) ?10 10 a i oz tri-stated i/o pin leakage current v o = 4.1 to ?0.5 v (13) ?10 10 a i cc0 v cc supply current (standby) (all esbs in power-down mode) v i = ground, no load, no toggling inputs, -1 speed grade 10 ma v i = ground, no load, no toggling inputs, -2, -3 speed grades 5ma r conf value of i/o pin pull-up resistor before and during configuration v ccio = 3.0 v (14) 20 50 k ? v ccio = 2.375 v (14) 30 80 k ? v ccio =1.71 v (14) 60 150 k ?
altera corporation 65 apex 20k programmable logic device family data sheet 1 for dc operating specifications on apex 20ke i/o standards, please refer to application note 117 (using selectable i/o standards in altera devices). notes to tables 27 through 30 : (1) see the operating requirements for altera devices data sheet . (2) minimum dc input is ?0.5 v. during transitions, the in puts may undershoot to ?2.0 v or overshoot to 5.75 v for input currents less than 100 ma and periods shorter than 20 ns. (3) numbers in parentheses are for industrial-temperature-range devices. (4) maximum v cc rise time is 100 ms, and v cc must rise monotonically. (5) minimum dc input is ?0.5 v. during transitions, the inpu ts may undershoot to ?2.0 v or overshoot to the voltage shown in the following table based on input duty cycle for input currents less than 100 ma. the overshoot is dependent upon duty cycle of the signal. the dc case is equivalent to 100% duty cycle. vin max. duty cycle 4.0v 100% (dc) 4.1 90% 4.2 50% 4.3 30% 4.4 17% 4.5 10% (6) all pins, including dedicated inputs, clock, i/o, and jtag pins, may be driven before v ccint and v ccio are powered. (7) typical values are for t a = 25 c, v ccint = 1.8 v, and v ccio = 1.8 v, 2.5 v or 3.3 v. (8) these values are specified under the apex 20ke device recommended operating condit ions, shown in table 24 on page 60. (9) refer to application note 117 (using selectable i/o standards in altera devices) for the v ih , v il , v oh , v ol , and i i parameters when vccio = 1.8 v. (10) the apex 20ke input buffers are compatible with 1.8-v, 2.5-v and 3.3-v (lvttl and lvcmos) signals. additionally, the input buffers are 3.3-v pci compliant. input buffers also meet specifications for gtl+, ctt, agp, sstl-2, sstl-3, and hstl. (11) the i oh parameter refers to high-level ttl, pci, or cmos output current. (12) the i ol parameter refers to low-level ttl, pci, or cmos outp ut current. this parameter a pplies to open-drain pins as well as output pins. (13) this value is specified for normal device operation. the value may vary during power-up. (14) pin pull-up resistance values will be lower if an external source drives the pin higher than v ccio . (15) capacitance is sample-tested only. figure 33 shows the relationship between v ccio and v ccint for 3.3-v pci compliance on apex 20k devices. table 30. apex 20ke device capacitance note (15) symbol parameter conditions min max unit c in input capacitance v in = 0 v, f = 1.0 mhz 8 pf c inclk input capacitance on dedicated clock pin v in = 0 v, f = 1.0 mhz 12 pf c out output capacitance v out = 0 v, f = 1.0 mhz 8 pf
66 altera corporation apex 20k programmable logic device family data sheet figure 33. relationship between v ccio & v ccint for 3.3-v pci compliance figure 34 shows the typical output driv e characteristics of apex 20k devices with 3.3-v and 2.5-v v ccio . the output driver is compatible with the 3.3-v pci local bus specification , revision 2.2 (when vccio pins are connected to 3.3 v). 5-v tolerant apex 20k devices in the -1 speed grade are 5-v pci compliant over all operating conditions. figure 34. output drive char acteristics of apex 20k device note (1) note to figure 34 : (1) these are transient (ac) currents. 3.0 3.1 3.3 v ccio 3.6 2.3 2.5 2.7 v ccint (v) (v) pci-compliant region v o output voltage (v) i ol i oh i oh v v v ccint = 2.5 v ccio = 2.5 room temperature v v v ccint = 2.5 v ccio = 3.3 room temperature 123 10 20 30 50 60 40 70 80 90 v o output voltage (v) 123 10 20 30 50 60 40 70 80 90 i ol o typical i output current (ma) o typical i output current (ma)
altera corporation 67 apex 20k programmable logic device family data sheet figure 35 shows the output drive characteristics of apex 20ke devices. figure 35. output drive characte ristics of apex 20ke devices note (1) note to figure 35 : (1) these are transient (ac) currents. timing model the high-performance fasttrack and megalab interconnect routing resources ensure predictable perfor mance, accurate simulation, and accurate timing analysis. this predictable performance contrasts with that of fpgas, which use a segmented co nnection scheme and therefore have unpredictable performance. vo output voltage (v) i ol i oh 2 4 6 8 10 12 14 16 18 20 22 24 26 vo output voltage (v) i ol i oh 5 10 15 20 45 0.5 1 1.5 2 2.5 3 25 30 35 40 50 55 60 typical i o output current (ma) 10 20 30 40 50 60 70 80 90 0.5 1 1.5 2 2.5 3 vo output voltage (v) v ccint = 1.8 v v ccio = 3.3 v room temperature i oh i ol typical i o output current (ma) 100 110 120 0.5 1 1.5 2.0 v ccint = 1.8 v v ccio = 2.5v room temperature v ccint = 1.8v v ccio = 1.8v room temperature typical i o output current (ma)
68 altera corporation apex 20k programmable logic device family data sheet all specifications are always represen tative of worst-case supply voltage and junction temperature conditions. all output-pin-timing specifications are reported for maximum driver strength. figure 36 shows the f max timing model for apex 20k devices. figure 36. apex 20k f max timing model figure 37 shows the f max timing model for apex 20ke devices. these parameters can be used to estimate f max for multiple levels of logic. quartus ii software timing analysis should be us ed for more accurate timing information. su h co lut t t t t t t t t t t t t t t t esbrc esbwc esbwesu esbdatasu esbaddrsu esbdataco1 esbdataco2 esbdd pd ptermsu ptermco t t t f1?4 f5?20 f20+ le esb routing delay
altera corporation 69 apex 20k programmable logic device family data sheet figure 37. apex 20ke f max timing model su h co lut t t t t t t t f1 4 f5 20 f20+ le routing delay t t t t t t t t t t t esbarc esbsrc esbswdsu esbdatasu t esbwaddrsu esbraddrsu esbdataco1 esbdataco2 esbdd t t t t esbwdh esbrasu esbrah esbwesu t esbweh pd ptermsu ptermco esb t esbsrasu t esbwdsu t esbwasu t esbswc t esbawc
70 altera corporation apex 20k programmable logic device family data sheet figures 38 and 39 show the asynchronous and synchronous timing waveforms, respectively, for the esb macroparameters in table 31 . figure 38. esb asynchronous timing waveforms esb asynchronous write esb asynchronous read re a0 d0 d3 t esbarc a1 a2 a3 d2 d1 rdaddress data-out we a0 din1 dout2 t esbdd a1 a2 din1 din0 t esbwccomb t esbwasu t esbwah t esbwdh t esbwdsu t esbwp din0 data-in wraddress data-out
altera corporation 71 apex 20k programmable logic device family data sheet figure 39. esb synchronous timing waveforms figure 40 shows the timing model for bidirectional i/o pin timing. we clk esb synchronous read a0 d2 t esbdatasu t esbarc t esbdataco2 a1 a2 a3 d1 t esbdatah a0 we clk dout0 din1 din2 din3 din2 t esbwesu t esbswc t esbweh t esbdataco1 a1 a2 a3 a2 din3 din2 din1 t esbdatah t esbdatasu esb synchronous write (esb output registers used) dout1 rdaddress data-out wraddress data-out data-in
72 altera corporation apex 20k programmable logic device family data sheet figure 40. synchronous bidire ctional pin external timing notes to figure 40 : (1) the output enable and input registers are le registers in the lab adjacent to a bidirectional row pin. the output enable register is set with ?output enable routing= signal-pin? option in the quartus ii software. (2) the lab adjacent input register is set with ?decrease input delay to internal cells= off?. this maintains a zero ho ld time for lab adjacent registers while giving a fast, position independent setup time. a faster se tup time with zero hold time is possible by setting ?decrease input delay to inte rnal cells= on? and moving the input register farther away from the bidirectiona l pin. the exact position where zero hold occurs with the minimum setup time, varie s with device density and speed grade. table 31 describes the f max timing parameters shown in figure 36 on page 68 . prn clrn dq prn clrn dq (1) ioe register bidirectional pin dedicated clock prn clrn dq (1) xzbidir t zxbidir t outcobidir t insubidir t inhbidir t oe register output ioe register input register (2) table 31. apex 20k f max timing parameters (part 1 of 2) symbol parameter t su le register setup time before clock t h le register hold time after clock t co le register cloc k-to-output delay t lut lut delay for data-in t esbrc esb asynchronous read cycle time t esbwc esb asynchronous write cycle time t esbwesu esb we setup time before clock when using input register t esbdatasu esb data setup time before clock when using input register t esbdatah esb data hold time after clock when using input register t esbaddrsu esb address setup time before cloc k when using input registers t esbdataco1 esb clock-to-output delay when using output registers
altera corporation 73 apex 20k programmable logic device family data sheet tables 32 and 33 describe apex 20k extern al timing parameters. t esbdataco2 esb clock-to-output delay without output registers t esbdd esb data-in to data-out delay for ram mode t pd esb macrocell input to non-registered output t ptermsu esb macrocell register setup time before clock t ptermco esb macrocell register clock-to-output delay t f1-4 fanout delay using local interconnect t f5-20 fanout delay using megalab interconnect t f20+ fanout delay using fasttrack interconnect t ch minimum clock high ti me from clock pin t cl minimum clock low time from clock pin t clrp le clear pulse width t prep le preset pulse width t esbch clock high time t esbcl clock low time t esbwp write pulse width t esbrp read pulse width table 31. apex 20k f max timing parameters (part 2 of 2) symbol parameter table 32. apex 20k external timing parameters note (1) symbol clock parameter t insu setup time with global clock at ioe register t inh hold time with global clock at ioe register t outco clock-to-output delay with global clock at ioe register table 33. apex 20k external bi directional timing parameters note (1) symbol parameter conditions t insubidir setup time for bidirectional pins with global clock at same-row or same- column le register t inhbidir hold time for bidirectional pins with global clock at same-row or same- column le register t outcobidir clock-to-output delay for bidirecti onal pins with gl obal clock at ioe register c1 = 10 pf t xzbidir synchronous ioe output buffer disable delay c1 = 10 pf t zxbidir synchronous ioe output buffer enable delay , slow slew rate = off c1 = 10 pf
74 altera corporation apex 20k programmable logic device family data sheet note to tables 32 and 33 : (1) these timing parameters are sample-tested only. tables 34 through 37 show apex 20ke le, esb, routing, and functional timing microparameters for the f max timing model. table 34. apex 20ke le timing microparameters symbol parameter t su le register setup time before clock t h le register hold time after clock t co le register clock-to-output delay t lut lut delay for data-in to data-out table 35. apex 20ke esb timing microparameters symbol parameter t esbarc esb asynchronous read cycle time t esbsrc esb synchronous read cycle time t esbawc esb asynchronous write cycle time t esbswc esb synchronous write cycle time t esbwasu esb write address setup time with respect to we t esbwah esb write address hold time with respect to we t esbwdsu esb data setup time with respect to we t esbwdh esb data hold time with respect to we t esbrasu esb read address setup time with respect to re t esbrah esb read address hold time with respect to re t esbwesu esb we setup time before clock when using input register t esbweh esb we hold time after clock when using input register t esbdatasu esb data setup time before cloc k when using input register t esbdatah esb data hold time after clock when using input register t esbwaddrsu esb write address setup time before clock when using input registers t esbraddrsu esb read address setup time before clock when using input registers t esbdataco1 esb clock-to-output delay when using output registers t esbdataco2 esb clock-to-output delay without output registers t esbdd esb data-in to data-out delay for ram mode t pd esb macrocell input to non-registered output t ptermsu esb macrocell register setup time before clock t ptermco esb macrocell register clock-to-output delay
altera corporation 75 apex 20k programmable logic device family data sheet note to table 36 : (1) these parameters are worst-case values fo r typical applications . post-compilation timing simulation and timing analysis are required to determine actual worst-case performance. tables 38 and 39 describe the apex 20ke ex ternal timing parameters. table 36. apex 20ke routing timing microparameters note (1) symbol parameter t f1-4 fanout delay using local interconnect t f5-20 fanout delay estimate using megalab interconnect t f20+ fanout delay estimate using fasttrack interconnect table 37. apex 20ke functional timing microparameters symbol parameter tch minimum clock high time from clock pin tcl minimum clock low time from clock pin tclrp le clear pulse width tprep le preset pulse width tesbch clock high time for esb tesbcl clock low time for esb tesbwp write pulse width tesbrp read pulse width table 38. apex 20ke external timing parameters note (1) symbol clock parameter conditions t insu setup time with global cl ock at ioe input register t inh hold time with global clock at ioe input register t outco clock-to-output delay wi th global clock at ioe output register c1 = 10 pf t insupll setup time with pll clock at ioe input register t inhpll hold time with pll clock at ioe input register t outcopll clock-to-output delay with pll cloc k at ioe output register c1 = 10 pf
76 altera corporation apex 20k programmable logic device family data sheet note to tables 38 and 39 : (1) these timing parameters are sample-tested only. table 39. apex 20ke external bi directional ti ming parameters note (1) symbol parameter conditions t insubidir setup time for bidirectional pins with global clock at lab adjacent input register t inhbidir hold time for bidirectional pins wi th global clock at lab adjacent input register t outcobidir clock-to-output delay for bidirectional pins with global clock at ioe output register c1 = 10 pf t xzbidir synchronous output enable register to output buffer disable delay c1 = 10 pf t zxbidir synchronous output enable register output buffer enable delay c1 = 10 pf t insubidirpll setup time for bidirectional pins wi th pll clock at lab adjacent input register t inhbidirpll hold time for bidirectional pins wi th pll clock at lab adjacent input register t outcobidirpll clock-to-output delay for bidirectional pins with pll clock at ioe output register c1 = 10 pf t xzbidirpll synchronous output enable register to output buffer disable delay with pll c1 = 10 pf t zxbidirpll synchronous output enable register output buffer enable delay with pll c1 = 10 pf
altera corporation 77 apex 20k programmable logic device family data sheet tables 40 through 42 show the f max timing parameters for ep20k100, ep20k200, and ep20k400 apex 20k devices. table 40. ep20k100 f max timing parameters symbol -1 speed grade -2 speed grade -3 speed grade units min max min max min max t su 0.5 0.6 0.8 ns t h 0.7 0.8 1.0 ns t co 0.3 0.4 0.5 ns t lut 0.8 1.0 1.3 ns t esbrc 1.7 2.1 2.4 ns t esbwc 5.7 6.9 8.1 ns t esbwesu 3.3 3.9 4.6 ns t esbdatasu 2.2 2.7 3.1 ns t esbdatah 0.6 0.8 0.9 ns t esbaddrsu 2.4 2.9 3.3 ns t esbdataco1 1.3 1.6 1.8 ns t esbdataco2 2.6 3.1 3.6 ns t esbdd 2.5 3.3 3.6 ns t pd 2.5 3.0 3.6 ns t ptermsu 2.3 2.6 3.2 ns t ptermco 1.5 1.8 2.1 ns t f1-4 0.5 0.6 0.7 ns t f5-20 1.6 1.7 1.8 ns t f20+ 2.2 2.2 2.3 ns t ch 2.0 2.5 3.0 ns t cl 2.0 2.5 3.0 ns t clrp 0.3 0.4 0.4 ns t prep 0.5 0.5 0.5 ns t esbch 2.0 2.5 3.0 ns t esbcl 2.0 2.5 3.0 ns t esbwp 1.6 1.9 2.2 ns t esbrp 1.0 1.3 1.4 ns
78 altera corporation apex 20k programmable logic device family data sheet table 41. ep20k200 f max timing parameters symbol -1 speed grade -2 speed grade -3 speed grade units min max min max min max t su 0.5 0.6 0.8 ns t h 0.7 0.8 1.0 ns t co 0.3 0.4 0.5 ns t lut 0.8 1.0 1.3 ns t esbrc 1.7 2.1 2.4 ns t esbwc 5.7 6.9 8.1 ns t esbwesu 3.3 3.9 4.6 ns t esbdatasu 2.2 2.7 3.1 ns t esbdatah 0.6 0.8 0.9 ns t esbaddrsu 2.4 2.9 3.3 ns t esbdataco1 1.3 1.6 1.8 ns t esbdataco2 2.6 3.1 3.6 ns t esbdd 2.5 3.3 3.6 ns t pd 2.5 3.0 3.6 ns t ptermsu 2.3 2.7 3.2 ns t ptermco 1.5 1.8 2.1 ns t f1-4 0.5 0.6 0.7 ns t f5-20 1.6 1.7 1.8 ns t f20+ 2.2 2.2 2.3 ns t ch 2.0 2.5 3.0 ns t cl 2.0 2.5 3.0 ns t clrp 0.3 0.4 0.4 ns t prep 0.4 0.5 0.5 ns t esbch 2.0 2.5 3.0 ns t esbcl 2.0 2.5 3.0 ns t esbwp 1.6 1.9 2.2 ns t esbrp 1.0 1.3 1.4 ns
altera corporation 79 apex 20k programmable logic device family data sheet tables 43 through 48 show the i/o external and external bidirectional timing parameter values for ep20k100, ep20k200, and ep20k400 apex 20k devices. table 42. ep20k400 f max timing parameters symbol -1 speed grade -2 speed grade -3 speed grade units minmaxminmaxminmax t su 0.1 0.3 0.6 ns t h 0.5 0.8 0.9 ns t co 0.1 0.4 0.6 ns t lut 1.0 1.2 1.4 ns t esbrc 1.7 2.1 2.4 ns t esbwc 5.7 6.9 8.1 ns t esbwesu 3.3 3.9 4.6 ns t esbdatasu 2.2 2.7 3.1 ns t esbdatah 0.6 0.8 0.9 ns t esbaddrsu 2.4 2.9 3.3 ns t esbdataco1 1.3 1.6 1.8 ns t esbdataco2 2.5 3.1 3.6 ns t esbdd 2.5 3.3 3.6 ns t pd 2.5 3.1 3.6 ns t ptermsu 1.7 2.1 2.4 ns t ptermco 1.0 1.2 1.4 ns t f1-4 0.4 0.5 0.6 ns t f5-20 2.6 2.8 2.9 ns t f20+ 3.7 3.8 3.9 ns t ch 2.0 2.5 3.0 ns t cl 2.0 2.5 3.0 ns t clrp 0.5 0.6 0.8 ns t prep 0.5 0.5 0.5 ns t esbch 2.0 2.5 3.0 ns t esbcl 2.0 2.5 3.0 ns t esbwp 1.5 1.9 2.2 ns t esbrp 1.0 1.2 1.4 ns
80 altera corporation apex 20k programmable logic device family data sheet table 43. ep20k100 external timing parameters symbol -1 speed grade -2 speed grade -3 speed grade unit min max min max min max t insu (1) 2.3 2.8 3.2 ns t inh (1) 0.0 0.0 0.0 ns t outco (1) 2.0 4.5 2.0 4.9 2.0 6.6 ns t insu (2) 1.1 1.2 ? ns t inh (2) 0.0 0.0 ? ns t outco (2) 0.5 2.7 0.5 3.1 ? 4.8 ns table 44. ep20k100 external bidi rectional timing parameters symbol -1 speed grade -2 speed grade -3 speed grade unit min max min max min max t insubidir (1) 2.3 2.8 3.2 ns t inhbidir (1) 0.0 0.0 0.0 ns t outcobidir (1) 2.0 4.5 2.0 4.9 2.0 6.6 ns t xzbidir (1) 5.0 5.9 6.9 ns t zxbidir (1) 5.0 5.9 6.9 ns t insubidir (2) 1.0 1.2 ? ns t inhbidir (2) 0.0 0.0 ? ns t outcobidir (2) 0.5 2.7 0.5 3.1 ? ? ns t xzbidir (2) 4.3 5.0 ? ns t zxbidir (2) 4.3 5.0 ? ns table 45. ep20k200 external timing parameters symbol -1 speed grade -2 speed grade -3 speed grade unit min max min max min max t insu (1) 1.9 2.3 2.6 ns t inh (1) 0.0 0.0 0.0 ns t outco (1) 2.0 4.6 2.0 5.6 2.0 6.8 ns t insu (2) 1.1 1.2 ? ns t inh (2) 0.0 0.0 ? ns t outco (2) 0.52.70.53.1 ? ?ns
altera corporation 81 apex 20k programmable logic device family data sheet table 46. ep20k200 external bidi rectional timing parameters symbol -1 speed grade -2 speed grade -3 speed grade unit min max min max min max t insubidir (1) 1.9 2.3 2.6 ns t inhbidir (1) 0.0 0.0 0.0 ns t outcobidir (1) 2.0 4.6 2.0 5.6 2.0 6.8 ns t xzbidir (1) 5.0 5.9 6.9 ns t zxbidir (1) 5.0 5.9 6.9 ns t insubidir (2) 1.1 1.2 ? ns t inhbidir (2) 0.0 0.0 ? ns t outcobidir (2) 0.5 2.7 0.5 3.1 ? ? ns t xzbidir (2) 4.3 5.0 ? ns t zxbidir (2) 4.3 5.0 ? ns table 47. ep20k400 external timing parameters symbol -1 speed grade -2 speed grade -3 speed grade unit min max min max min max t insu (1) 1.4 1.8 2.0 ns t inh (1) 0.0 0.0 0.0 ns t outco (1) 2.0 4.9 2.0 6.1 2.0 7.0 ns t insu (2) 0.4 1.0 ? ns t inh (2) 0.0 0.0 ? ns t outco (2) 0.5 3.1 0.5 4.1 ? ? ns table 48. ep20k400 external bidi rectional timing parameters symbol -1 speed grade -2 speed grade -3 speed grade unit min max min max min max t insubidir (1) 1.4 1.8 2.0 ns t inhbidir (1) 0.0 0.0 0.0 ns t outcobidir (1) 2.0 4.9 2.0 6.1 2.0 7.0 ns t xzbidir (1) 7.3 8.9 10.3 ns t zxbidir (1) 7.3 8.9 10.3 ns t insubidir (2) 0.5 1.0 ? ns t inhbidir (2) 0.0 0.0 ? ns t outcobidir (2) 0.5 3.1 0.5 4.1 ? ? ns t xzbidir (2) 6.2 7.6 ? ns t zxbidir (2) 6.2 7.6 ? ns
82 altera corporation apex 20k programmable logic device family data sheet notes to tables 43 through 48 : (1) this parameter is measured without using clocklock or clockboost circuits. (2) this parameter is measured using clocklock or clockboost circuits. tables 49 through 54 describe f max le timing micr oparameters, f max esb timing microparameters, f max routing delays, minimum pulse width timing parameters, external timing parameters, and external bidirectional timing parameters for ep20k30e apex 20ke devices. table 49. ep20k30e f max le timing microparameters symbol -1 -2 -3 unit min max min max min max t su 0.01 0.02 0.02 ns t h 0.11 0.16 0.23 ns t co 0.32 0.45 0.67 ns t lut 0.85 1.20 1.77 ns
altera corporation 83 apex 20k programmable logic device family data sheet table 50. ep20k30e f max esb timing microparameters symbol -1 -2 -3 unit min max min max min max t esbarc 2.03 2.86 4.24 ns t esbsrc 2.58 3.49 5.02 ns t esbawc 3.88 5.45 8.08 ns t esbswc 4.08 5.35 7.48 ns t esbwasu 1.77 2.49 3.68 ns t esbwah 0.00 0.00 0.00 ns t esbwdsu 1.95 2.74 4.05 ns t esbwdh 0.00 0.00 0.00 ns t esbrasu 1.96 2.75 4.07 ns t esbrah 0.00 0.00 0.00 ns t esbwesu 1.80 2.73 4.28 ns t esbweh 0.00 0.00 0.00 ns t esbdatasu 0.07 0.48 1.17 ns t esbdatah 0.13 0.13 0.13 ns t esbwaddrsu 0.30 0.80 1.64 ns t esbraddrsu 0.37 0.90 1.78 ns t esbdataco1 1.11 1.32 1.67 ns t esbdataco2 2.65 3.73 5.53 ns t esbdd 3.88 5.45 8.08 ns t pd 1.91 2.69 3.98 ns t ptermsu 1.04 1.71 2.82 ns t ptermco 1.13 1.34 1.69 ns table 51. ep20k30e f max routing delays symbol -1 -2 -3 unit min max min max min max t f1-4 0.24 0.27 0.31 ns t f5-20 1.03 1.14 1.30 ns t f20+ 1.42 1.54 1.77 ns
84 altera corporation apex 20k programmable logic device family data sheet table 52. ep20k30e minimum pulse width timing parameters symbol -1 -2 -3 unit min max min max min max t ch 0.55 0.78 1.15 ns t cl 0.55 0.78 1.15 ns t clrp 0.22 0.31 0.46 ns t prep 0.22 0.31 0.46 ns t esbch 0.55 0.78 1.15 ns t esbcl 0.55 0.78 1.15 ns t esbwp 1.43 2.01 2.97 ns t esbrp 1.15 1.62 2.39 ns table 53. ep20k30e external timing parameters symbol -1 -2 -3 unit min max min max min max t insu 2.02 2.13 2.24 ns t inh 0.00 0.00 0.00 ns t outco 2.00 4.88 2.00 5.36 2.00 5.88 ns t insupll 2.11 2.23 - ns t inhpll 0.00 0.00 - ns t outcopll 0.50 2.60 0.50 2.88 - - ns table 54. ep20k30e external bi directional timing parameters symbol -1 -2 -3 unit min max min max min max t insubidir 1.85 1.77 1.54 ns t inhbidir 0.00 0.00 0.00 ns t outcobidir 2.00 4.88 2.00 5.36 2.00 5.88 ns t xzbidir 7.48 8.46 9.83 ns t zxbidir 7.48 8.46 9.83 ns t insubidirpll 4.12 4.24 - ns t inhbidirpll 0.00 0.00 - ns t outcobidirpll 0.50 2.60 0.50 2.88 - - ns t xzbidirpll 5.21 5.99 - ns t zxbidirpll 5.21 5.99 - ns
altera corporation 85 apex 20k programmable logic device family data sheet tables 55 through 60 describe f max le timing micr oparameters, f max esb timing microparameters, f max routing delays, minimum pulse width timing parameters, external timing parameters, and external bidirectional timing parameters for ep20k60e apex 20ke devices. table 55. ep20k60e f max le timing microparameters symbol -1 -2 -3 unit min max min max min max t su 0.17 0.15 0.16 ns t h 0.32 0.33 0.39 ns t co 0.29 0.40 0.60 ns t lut 0.77 1.07 1.59 ns
86 altera corporation apex 20k programmable logic device family data sheet table 56. ep20k60e f max esb timing microparameters symbol -1 -2 -3 unit min max min max min max t esbarc 1.83 2.57 3.79 ns t esbsrc 2.46 3.26 4.61 ns t esbawc 3.50 4.90 7.23 ns t esbswc 3.77 4.90 6.79 ns t esbwasu 1.59 2.23 3.29 ns t esbwah 0.00 0.00 0.00 ns t esbwdsu 1.75 2.46 3.62 ns t esbwdh 0.00 0.00 0.00 ns t esbrasu 1.76 2.47 3.64 ns t esbrah 0.00 0.00 0.00 ns t esbwesu 1.68 2.49 3.87 ns t esbweh 0.00 0.00 0.00 ns t esbdatasu 0.08 0.43 1.04 ns t esbdatah 0.13 0.13 0.13 ns t esbwaddrsu 0.29 0.72 1.46 ns t esbraddrsu 0.36 0.81 1.58 ns t esbdataco1 1.06 1.24 1.55 ns t esbdataco2 2.39 3.35 4.94 ns t esbdd 3.50 4.90 7.23 ns t pd 1.72 2.41 3.56 ns t ptermsu 0.99 1.56 2.55 ns t ptermco 1.07 1.26 1.08 ns
altera corporation 87 apex 20k programmable logic device family data sheet table 57. ep20k60e f max routing delays symbol -1 -2 -3 unit min max min max min max t f1-4 0.24 0.26 0.30 ns t f5-20 1.45 1.58 1.79 ns t f20+ 1.96 2.14 2.45 ns table 58. ep20k60e minimum puls e width timing parameters symbol -1 -2 -3 unit min max min max min max t ch 2.00 2.50 2.75 ns t cl 2.00 2.50 2.75 ns t clrp 0.20 0.28 0.41 ns t prep 0.20 0.28 0.41 ns t esbch 2.00 2.50 2.75 ns t esbcl 2.00 2.50 2.75 ns t esbwp 1.29 1.80 2.66 ns t esbrp 1.04 1.45 2.14 ns table 59. ep20k60e external timing parameters symbol -1 -2 -3 unit min max min max min max t insu 2.03 2.12 2.23 ns t inh 0.00 0.00 0.00 ns t outco 2.00 4.84 2.00 5.31 2.00 5.81 ns t insupll 1.12 1.15 - ns t inhpll 0.00 0.00 - ns t outcopll 0.50 3.37 0.50 3.69 - - ns
88 altera corporation apex 20k programmable logic device family data sheet tables 61 through 66 describe f max le timing microparameters, f max esb timing microparameters, f max routing delays, minimum pulse width timing parameters, ex ternal timing parameters, and external bidirectio nal timing parameters for ep20k100e apex 20ke devices. table 60. ep20k60e external bidi rectional timing parameters symbol -1 -2 -3 unit min max min max min max t insubidir 2.77 2.91 3.11 ns t inhbidir 0.00 0.00 0.00 ns t outcobidir 2.00 4.84 2.00 5.31 2.00 5.81 ns t xzbidir 6.47 7.44 8.65 ns t zxbidir 6.47 7.44 8.65 ns t insubidirpll 3.44 3.24 - ns t inhbidirpll 0.00 0.00 - ns t outcobidirpll 0.50 3.37 0.50 3.69 - - ns t xzbidirpll 5.00 5.82 - ns t zxbidirpll 5.00 5.82 - ns table 61. ep20k100e f max le timing microparameters symbol -1 -2 -3 unit min max min max min max t su 0.25 0.25 0.25 ns t h 0.25 0.25 0.25 ns t co 0.28 0.28 0.34 ns t lut 0.80 0.95 1.13 ns
altera corporation 89 apex 20k programmable logic device family data sheet table 62. ep20k100e f max esb timing microparameters symbol -1 -2 -3 unit min max min max min max t esbarc 1.61 1.84 1.97 ns t esbsrc 2.57 2.97 3.20 ns t esbawc 0.52 4.09 4.39 ns t esbswc 3.17 3.78 4.09 ns t esbwasu 0.56 6.41 0.63 ns t esbwah 0.48 0.54 0.55 ns t esbwdsu 0.71 0.80 0.81 ns t esbwdh .048 0.54 0.55 ns t esbrasu 1.57 1.75 1.87 ns t esbrah 0.00 0.00 0.20 ns t esbwesu 1.54 1.72 1.80 ns t esbweh 0.00 0.00 0.00 ns t esbdatasu -0.16 -0.20 -0.20 ns t esbdatah 0.13 0.13 0.13 ns t esbwaddrsu 0.12 0.08 0.13 ns t esbraddrsu 0.17 0.15 0.19 ns t esbdataco1 1.20 1.39 1.52 ns t esbdataco2 2.54 2.99 3.22 ns t esbdd 3.06 3.56 3.85 ns t pd 1.73 2.02 2.20 ns t ptermsu 1.11 1.26 1.38 ns t ptermco 1.19 1.40 1.08 ns table 63. ep20k100e f max routing delays symbol -1 -2 -3 unit min max min max min max t f1-4 0.24 0.27 0.29 ns t f5-20 1.04 1.26 1.52 ns t f20+ 1.12 1.36 1.86 ns
90 altera corporation apex 20k programmable logic device family data sheet table 64. ep20k100e minimum pulse width timing parameters symbol -1 -2 -3 unit min max min max min max t ch 2.00 2.00 2.00 ns t cl 2.00 2.00 2.00 ns t clrp 0.20 0.20 0.20 ns t prep 0.20 0.20 0.20 ns t esbch 2.00 2.00 2.00 ns t esbcl 2.00 2.00 2.00 ns t esbwp 1.29 1.53 1.66 ns t esbrp 1.11 1.29 1.41 ns table 65. ep20k100e external timing parameters symbol -1 -2 -3 unit min max min max min max t insu 2.23 2.32 2.43 ns t inh 0.00 0.00 0.00 ns t outco 2.00 4.86 2.00 5.35 2.00 5.84 ns t insupll 1.58 1.66 - ns t inhpll 0.00 0.00 - ns t outcopll 0.50 2.96 0.50 3.29 - - ns table 66. ep20k100e external bidirectional timing parameters symbol -1 -2 -3 unit min max min max min max t insubidir 2.74 2.96 3.19 ns t inhbidir 0.00 0.00 0.00 ns t outcobidir 2.00 4.86 2.00 5.35 2.00 5.84 ns t xzbidir 5.00 5.48 5.89 ns t zxbidir 5.00 5.48 5.89 ns t insubidirpll 4.64 5.03 - ns t inhbidirpll 0.00 0.00 - ns t outcobidirpll 0.50 2.96 0.50 3.29 - - ns t xzbidirpll 3.10 3.42 - ns t zxbidirpll 3.10 3.42 - ns
altera corporation 91 apex 20k programmable logic device family data sheet tables 67 through 72 describe f max le timing microparameters, f max esb timing microparameters, f max routing delays, minimum pulse width timing parameters, ex ternal timing parameters, and external bidirectiona l timing parameters for ep20k160e apex 20ke devices. table 67. ep20k160e f max le timing microparameters symbol -1 -2 -3 unit min max min max min max t su 0.22 0.24 0.26 ns t h 0.22 0.24 0.26 ns t co 0.25 0.31 0.35 ns t lut 0.69 0.88 1.12 ns
92 altera corporation apex 20k programmable logic device family data sheet table 68. ep20k160e f max esb timing microparameters symbol -1 -2 -3 unit min max min max min max t esbarc 1.65 2.02 2.11 ns t esbsrc 2.21 2.70 3.11 ns t esbawc 3.04 3.79 4.42 ns t esbswc 2.81 3.56 4.10 ns t esbwasu 0.54 0.66 0.73 ns t esbwah 0.36 0.45 0.47 ns t esbwdsu 0.68 0.81 0.94 ns t esbwdh 0.36 0.45 0.47 ns t esbrasu 1.58 1.87 2.06 ns t esbrah 0.00 0.00 0.01 ns t esbwesu 1.41 1.71 2.00 ns t esbweh 0.00 0.00 0.00 ns t esbdatasu -0.02 -0.03 0.09 ns t esbdatah 0.13 0.13 0.13 ns t esbwaddrsu 0.14 0.17 0.35 ns t esbraddrsu 0.21 0.27 0.43 ns t esbdataco1 1.04 1.30 1.46 ns t esbdataco2 2.15 2.70 3.16 ns t esbdd 2.69 3.35 3.97 ns t pd 1.55 1.93 2.29 ns t ptermsu 1.01 1.23 1.52 ns t ptermco 1.06 1.32 1.04 ns
altera corporation 93 apex 20k programmable logic device family data sheet table 69. ep20k160e f max routing delays symbol -1 -2 -3 unit min max min max min max t f1-4 0.25 0.26 0.28 ns t f5-20 1.00 1.18 1.35 ns t f20+ 1.95 2.19 2.30 ns table 70. ep20k160e minimum puls e width timing parameters symbol -1 -2 -3 unit min max min max min max t ch 1.34 1.43 1.55 ns t cl 1.34 1.43 1.55 ns t clrp 0.18 0.19 0.21 ns t prep 0.18 0.19 0.21 ns t esbch 1.34 1.43 1.55 ns t esbcl 1.34 1.43 1.55 ns t esbwp 1.15 1.45 1.73 ns t esbrp 0.93 1.15 1.38 ns table 71. ep20k160e exter nal timing parameters symbol -1 -2 -3 unit min max min max min max t insu 2.23 2.34 2.47 ns t inh 0.00 0.00 0.00 ns t outco 2.00 5.07 2.00 5.59 2.00 6.13 ns t insupll 2.12 2.07 - ns t inhpll 0.00 0.00 - ns t outcopll 0.50 3.00 0.50 3.35 - - ns
94 altera corporation apex 20k programmable logic device family data sheet tables 73 through 78 describe f max le timing micr oparameters, f max esb timing microparameters, f max routing delays, minimum pulse width timing parameters, external timing parameters, and external bidirectional timing parameters for ep20k200e apex 20ke devices. table 72. ep20k160e external bidirectional timing parameters symbol -1 -2 -3 unit min max min max min max t insubidir 2.86 3.24 3.54 ns t inhbidir 0.00 0.00 0.00 ns t outcobidir 2.00 5.07 2.00 5.59 2.00 6.13 ns t xzbidir 7.43 8.23 8.58 ns t zxbidir 7.43 8.23 8.58 ns t insubidirpll 4.93 5.48 - ns t inhbidirpll 0.00 0.00 - ns t outcobidirpll 0.50 3.00 0.50 3.35 - - ns t xzbidirpll 5.36 5.99 - ns t zxbidirpll 5.36 5.99 - ns table 73. ep20k200e f max le timing microparameters symbol -1 -2 -3 unit min max min max min max t su 0.23 0.24 0.26 ns t h 0.23 0.24 0.26 ns t co 0.26 0.31 0.36 ns t lut 0.70 0.90 1.14 ns
altera corporation 95 apex 20k programmable logic device family data sheet table 74. ep20k200e f max esb timing microparameters symbol -1 -2 -3 unit min max min max min max t esbarc 1.68 2.06 2.24 ns t esbsrc 2.27 2.77 3.18 ns t esbawc 3.10 3.86 4.50 ns t esbswc 2.90 3.67 4.21 ns t esbwasu 0.55 0.67 0.74 ns t esbwah 0.36 0.46 0.48 ns t esbwdsu 0.69 0.83 0.95 ns t esbwdh 0.36 0.46 0.48 ns t esbrasu 1.61 1.90 2.09 ns t esbrah 0.00 0.00 0.01 ns t esbwesu 1.42 1.71 2.01 ns t esbweh 0.00 0.00 0.00 ns t esbdatasu -0.06 -0.07 0.05 ns t esbdatah 0.13 0.13 0.13 ns t esbwaddrsu 0.11 0.13 0.31 ns t esbraddrsu 0.18 0.23 0.39 ns t esbdataco1 1.09 1.35 1.51 ns t esbdataco2 2.19 2.75 3.22 ns t esbdd 2.75 3.41 4.03 ns t pd 1.58 1.97 2.33 ns t ptermsu 1.00 1.22 1.51 ns t ptermco 1.10 1.37 1.09 ns table 75. ep20k200e f max routing delays symbol -1 -2 -3 unit min max min max min max t f1-4 0.25 0.27 0.29 ns t f5-20 1.02 1.20 1.41 ns t f20+ 1.99 2.23 2.53 ns
96 altera corporation apex 20k programmable logic device family data sheet table 76. ep20k200e minimum pulse width timing parameters symbol -1 -2 -3 unit min max min max min max t ch 1.36 2.44 2.65 ns t cl 1.36 2.44 2.65 ns t clrp 0.18 0.19 0.21 ns t prep 0.18 0.19 0.21 ns t esbch 1.36 2.44 2.65 ns t esbcl 1.36 2.44 2.65 ns t esbwp 1.18 1.48 1.76 ns t esbrp 0.95 1.17 1.41 ns table 77. ep20k200e external timing parameters symbol -1 -2 -3 unit min max min max min max t insu 2.24 2.35 2.47 ns t inh 0.00 0.00 0.00 ns t outco 2.00 5.12 2.00 5.62 2.00 6.11 ns t insupll 2.13 2.07 - ns t inhpll 0.00 0.00 - ns t outcopll 0.50 3.01 0.50 3.36 - - ns
altera corporation 97 apex 20k programmable logic device family data sheet tables 79 through 84 describe f max le timing micr oparameters, f max esb timing microparameters, f max routing delays, minimum pulse width timing parameters, external timing parameters, and external bidirectional timing parameters for ep20k300e apex 20ke devices. table 78. ep20k200e external bidi rectional timing parameters symbol -1 -2 -3 unit min max min max min max t insubidir 2.81 3.19 3.54 ns t inhbidir 0.00 0.00 0.00 ns t outcobidir 2.00 5.12 2.00 5.62 2.00 6.11 ns t xzbidir 7.51 8.32 8.67 ns t zxbidir 7.51 8.32 8.67 ns t insubidirpll 3.30 3.64 - ns t inhbidirpll 0.00 0.00 - ns t outcobidirpll 0.50 3.01 0.50 3.36 - - ns t xzbidirpll 5.40 6.05 - ns t zxbidirpll 5.40 6.05 - ns table 79. ep20k300e f max le timing microparameters symbol -1 -2 -3 unit min max min max min max t su 0.16 0.17 0.18 ns t h 0.31 0.33 0.38 ns t co 0.28 0.38 0.51 ns t lut 0.79 1.07 1.43 ns
98 altera corporation apex 20k programmable logic device family data sheet table 80. ep20k300e f max esb timing microparameters symbol -1 -2 -3 unit min max min max min max t esbarc 1.79 2.44 3.25 ns t esbsrc 2.40 3.12 4.01 ns t esbawc 3.41 4.65 6.20 ns t esbswc 3.68 4.68 5.93 ns t esbwasu 1.55 2.12 2.83 ns t esbwah 0.00 0.00 0.00 ns t esbwdsu 1.71 2.33 3.11 ns t esbwdh 0.00 0.00 0.00 ns t esbrasu 1.72 2.34 3.13 ns t esbrah 0.00 0.00 0.00 ns t esbwesu 1.63 2.36 3.28 ns t esbweh 0.00 0.00 0.00 ns t esbdatasu 0.07 0.39 0.80 ns t esbdatah 0.13 0.13 0.13 ns t esbwaddrsu 0.27 0.67 1.17 ns t esbraddrsu 0.34 0.75 1.28 ns t esbdataco1 1.03 1.20 1.40 ns t esbdataco2 2.33 3.18 4.24 ns t esbdd 3.41 4.65 6.20 ns t pd 1.68 2.29 3.06 ns t ptermsu 0.96 1.48 2.14 ns t ptermco 1.05 1.22 1.42 ns table 81. ep20k300e f max routing delays symbol -1 -2 -3 unit min max min max min max t f1-4 0.22 0.24 0.26 ns t f5-20 1.33 1.43 1.58 ns t f20+ 3.63 3.93 4.35 ns
altera corporation 99 apex 20k programmable logic device family data sheet table 82. ep20k300e minimum puls e width timing parameters symbol -1 -2 -3 unit min max min max min max t ch 1.25 1.43 1.67 ns t cl 1.25 1.43 1.67 ns t clrp 0.19 0.26 0.35 ns t prep 0.19 0.26 0.35 ns t esbch 1.25 1.43 1.67 ns t esbcl 1.25 1.43 1.67 ns t esbwp 1.25 1.71 2.28 ns t esbrp 1.01 1.38 1.84 ns table 83. ep20k300e exter nal timing parameters symbol -1 -2 -3 unit min max min max min max t insu 2.31 2.44 2.57 ns t inh 0.00 0.00 0.00 ns t outco 2.00 5.29 2.00 5.82 2.00 6.24 ns t insupll 1.76 1.85 - ns t inhpll 0.00 0.00 - ns t outcopll 0.50 2.65 0.50 2.95 - - ns table 84. ep20k300e external bidi rectional timing parameters symbol -1 -2 -3 unit min max min max min max t insubidir 2.77 2.85 3.11 ns t inhbidir 0.00 0.00 0.00 ns t outcobidir 2.00 5.29 2.00 5.82 2.00 6.24 ns t xzbidir 7.59 8.30 9.09 ns t zxbidir 7.59 8.30 9.09 ns t insubidirpll 2.50 2.76 - ns t inhbidirpll 0.00 0.00 - ns t outcobidirpll 0.50 2.65 0.50 2.95 - - ns t xzbidirpll 5.00 5.43 - ns t zxbidirpll 5.00 5.43 - ns
100 altera corporation apex 20k programmable logic device family data sheet tables 85 through 90 describe f max le timing micr oparameters, f max esb timing microparameters, f max routing delays, minimum pulse width timing parameters, external timing parameters, and external bidirectional timing parameters for EP20K400E apex 20ke devices. table 85. EP20K400E f max le timing microparameters symbol -1 speed grade -2 speed grade -3 speed grade unit min max min max min max t su 0.23 0.23 0.23 ns t h 0.23 0.23 0.23 ns t co 0.25 0.29 0.32 ns t lut 0.70 0.83 1.01 ns
altera corporation 101 apex 20k programmable logic device family data sheet table 86. EP20K400E f max esb timing microparameters symbol -1 speed grade -2 speed grade -3 speed grade unit min max min max min max t esbarc 1.67 1.91 1.99 ns t esbsrc 2.30 2.66 2.93 ns t esbawc 3.09 3.58 3.99 ns t esbswc 3.01 3.65 4.05 ns t esbwasu 0.54 0.63 0.65 ns t esbwah 0.36 0.43 0.42 ns t esbwdsu 0.69 0.77 0.84 ns t esbwdh 0.36 0.43 0.42 ns t esbrasu 1.61 1.77 1.86 ns t esbrah 0.00 0.00 0.01 ns t esbwesu 1.35 1.47 1.61 ns t esbweh 0.00 0.00 0.00 ns t esbdatasu -0.18 -0.30 -0.27 ns t esbdatah 0.13 0.13 0.13 ns t esbwaddrsu -0.02 -0.11 -0.03 ns t esbraddrsu 0.06 -0.01 -0.05 ns t esbdataco1 1.16 1.40 1.54 ns t esbdataco2 2.18 2.55 2.85 ns t esbdd 2.73 3.17 3.58 ns t pd 1.57 1.83 2.07 ns t ptermsu 0.92 0.99 1.18 ns t ptermco 1.18 1.43 1.17 ns
102 altera corporation apex 20k programmable logic device family data sheet table 87. EP20K400E f max routing delays symbol -1 speed grade -2 speed grade -3 speed grade unit min max min max min max t f1-4 0.25 0.25 0.26 ns t f5-20 1.01 1.12 1.25 ns t f20+ 3.71 3.92 4.17 ns table 88. EP20K400E minimum pulse width timing parameters symbol -1 speed grade -2 speed grade -3 speed grade unit min max min max min max t ch 1.36 2.22 2.35 ns t cl 1.36 2.26 2.35 ns t clrp 0.18 0.18 0.19 ns t prep 0.18 0.18 0.19 ns t esbch 1.36 2.26 2.35 ns t esbcl 1.36 2.26 2.35 ns t esbwp 1.17 1.38 1.56 ns t esbrp 0.94 1.09 1.25 ns table 89. EP20K400E external timing parameters symbol -1 speed grade -2 speed grade -3 speed grade unit min max min max min max t insu 2.51 2.64 2.77 ns t inh 0.00 0.00 0.00 ns t outco 2.00 5.25 2.00 5.79 2.00 6.32 ns t insupll 3.221 3.38 - ns t inhpll 0.00 0.00 - ns t outcopll 0.50 2.25 0.50 2.45 - - ns
altera corporation 103 apex 20k programmable logic device family data sheet tables 91 through 96 describe f max le timing micr oparameters, f max esb timing microparameters, f max routing delays, minimum pulse width timing parameters, external timing parameters, and external bidirectional timing parameters for ep20k600e apex 20ke devices. table 90. EP20K400E external bidi rectional timing parameters symbol -1 speed grade -2 speed grade -3 speed grade unit min max min max min max t insubidir 2.93 3.23 3.44 ns t inhbidir 0.00 0.00 0.00 ns t outcobidir 2.00 5.25 2.00 5.79 2.00 6.32 ns t xzbidir 5.95 6.77 7.12 ns t zxbidir 5.95 6.77 7.12 ns t insubidirpll 4.31 4.76 - ns t inhbidirpll 0.00 0.00 - ns t outcobidirpll 0.50 2.25 0.50 2.45 - - ns t xzbidirpll 2.94 3.43 - ns t zxbidirpll 2.94 3.43 - ns table 91. ep20k600e f max le timing microparameters symbol -1 speed grade -2 speed grade -3 speed grade unit min max min max min max t su 0.16 0.16 0.17 ns t h 0.29 0.33 0.37 ns t co 0.65 0.38 0.49 ns t lut 0.70 1.00 1.30 ns
104 altera corporation apex 20k programmable logic device family data sheet table 92. ep20k600e f max esb timing microparameters symbol -1 speed grade -2 speed grade -3 speed grade unit min max min max min max t esbarc 1.67 2.39 3.11 ns t esbsrc 2.27 3.07 3.86 ns t esbawc 3.19 4.56 5.93 ns t esbswc 3.51 4.62 5.72 ns t esbwasu 1.46 2.08 2.70 ns t esbwah 0.00 0.00 0.00 ns t esbwdsu 1.60 2.29 2.97 ns t esbwdh 0.00 0.00 0.00 ns t esbrasu 1.61 2.30 2.99 ns t esbrah 0.00 0.00 0.00 ns t esbwesu 1.49 2.30 3.11 ns t esbweh 0.00 0.00 0.00 ns t esbdatasu -0.01 0.35 0.71 ns t esbdatah 0.13 0.13 0.13 ns t esbwaddrsu 0.19 0.62 1.06 ns t esbraddrsu 0.25 0.71 1.17 ns t esbdataco1 1.01 1.19 1.37 ns t esbdataco2 2.18 3.12 4.05 ns t esbdd 3.19 4.56 5.93 ns t pd 1.57 2.25 2.92 ns t ptermsu 0.85 1.43 2.01 ns t ptermco 1.03 1.21 1.39 ns table 93. ep20k600e f max routing delays symbol -1 speed grade -2 speed grade -3 speed grade unit min max min max min max t f1-4 0.22 0.25 0.26 ns t f5-20 1.26 1.39 1.52 ns t f20+ 3.51 3.88 4.26 ns
altera corporation 105 apex 20k programmable logic device family data sheet table 94. ep20k600e minimum puls e width timing parameters symbol -1 speed grade -2 speed grade -3 speed grade unit min max min max min max t ch 2.00 2.50 2.75 ns t cl 2.00 2.50 2.75 ns t clrp 0.18 0.26 0.34 ns t prep 0.18 0.26 0.34 ns t esbch 2.00 2.50 2.75 ns t esbcl 2.00 2.50 2.75 ns t esbwp 1.17 1.68 2.18 ns t esbrp 0.95 1.35 1.76 ns table 95. ep20k600e exter nal timing parameters symbol -1 speed grade -2 speed grade -3 speed grade unit min max min max min max t insu 2.74 2.74 2.87 ns t inh 0.00 0.00 0.00 ns t outco 2.00 5.51 2.00 6.06 2.00 6.61 ns t insupll 1.86 1.96 - ns t inhpll 0.00 0.00 - ns t outcopll 0.50 2.62 0.50 2.91 - - ns table 96. ep20k600e external bidi rectional timing parameters symbol -1 speed grade -2 speed grade -3 speed grade unit min max min max min max t insubidir 0.64 0.98 1.08 ns t inhbidir 0.00 0.00 0.00 ns t outcobidir 2.00 5.51 2.00 6.06 2.00 6.61 ns t xzbidir 6.10 6.74 7.10 ns t zxbidir 6.10 6.74 7.10 ns t insubidirpll 2.26 2.68 - ns t inhbidirpll 0.00 0.00 - ns t outcobidirpll 0.50 2.62 0.50 2.91 - - ns t xzbidirpll 3.21 3.59 - ns t zxbidirpll 3.21 3.59 - ns
106 altera corporation apex 20k programmable logic device family data sheet tables 97 through 102 describe f max le timing micr oparameters, f max esb timing microparameters, f max routing delays, minimum pulse width timing parameters, external timing parameters, and external bidirectional timing parameters for ep20k1000e apex 20ke devices. table 97. ep20k1000e f max le timing microparameters symbol -1 speed grade -2 speed grade -3 speed grade unit min max min max min max t su 0.25 0.25 0.25 ns t h 0.25 0.25 0.25 ns t co 0.28 0.32 0.33 ns t lut 0.80 0.95 1.13 ns
altera corporation 107 apex 20k programmable logic device family data sheet table 98. ep20k1000e f max esb timing microparameters symbol -1 speed grade -2 speed grade -3 speed grade unit min max min max min max t esbarc 1.78 2.02 1.95 ns t esbsrc 2.52 2.91 3.14 ns t esbawc 3.52 4.11 4.40 ns t esbswc 3.23 3.84 4.16 ns t esbwasu 0.62 0.67 0.61 ns t esbwah 0.41 0.55 0.55 ns t esbwdsu 0.77 0.79 0.81 ns t esbwdh 0.41 0.55 0.55 ns t esbrasu 1.74 1.92 1.85 ns t esbrah 0.00 0.01 0.23 ns t esbwesu 2.07 2.28 2.41 ns t esbweh 0.00 0.00 0.00 ns t esbdatasu 0.25 0.27 0.29 ns t esbdatah 0.13 0.13 0.13 ns t esbwaddrsu 0.11 0.04 0.11 ns t esbraddrsu 0.14 0.11 0.16 ns t esbdataco1 1.29 1.50 1.63 ns t esbdataco2 2.55 2.99 3.22 ns t esbdd 3.12 3.57 3.85 ns t pd 1.84 2.13 2.32 ns t ptermsu 1.08 1.19 1.32 ns t ptermco 1.31 1.53 1.66 ns
108 altera corporation apex 20k programmable logic device family data sheet table 99. ep20k1000e f max routing delays symbol -1 speed grade -2 speed grade -3 speed grade unit min max min max min max t f1-4 0.27 0.27 0.27 ns t f5-20 1.45 1.63 1.75 ns t f20+ 4.15 4.33 4.97 ns table 100. ep20k1000e minimum pulse width timing parameters symbol -1 speed grade -2 speed grade -3 speed grade unit min max min max min max t ch 1.25 1.43 1.67 ns t cl 1.25 1.43 1.67 ns t clrp 0.20 0.20 0.20 ns t prep 0.20 0.20 0.20 ns t esbch 1.25 1.43 1.67 ns t esbcl 1.25 1.43 1.67 ns t esbwp 1.28 1.51 1.65 ns t esbrp 1.11 1.29 1.41 ns table 101. ep20k1000e external timing parameters symbol -1 speed grade -2 speed grade -3 speed grade unit min max min max min max t insu 2.70 2.84 2.97 ns t inh 0.00 0.00 0.00 ns t outco 2.00 5.75 2.00 6.33 2.00 6.90 ns t insupll 1.64 2.09 - ns t inhpll 0.00 0.00 - ns t outcopll 0.50 2.25 0.50 2.99 - - ns
altera corporation 109 apex 20k programmable logic device family data sheet tables 103 through 108 describe f max le timing micr oparameters, f max esb timing microparameters, f max routing delays, minimum pulse width timing parameters, external timing parameters, and external bidirectional timing parameters for ep20k1500e apex 20ke devices. table 102. ep20k1000e external bidirectional timing parameters symbol -1 speed grade -2 speed grade -3 speed grade unit min max min max min max t insubidir 3.22 3.33 3.51 ns t inhbidir 0.00 0.00 0.00 ns t outcobidir 2.00 5.75 2.00 6.33 2.00 6.90 ns t xzbidir 6.31 7.09 7.76 ns t zxbidir 6.31 7.09 7.76 ns t insubidirpl l 3.25 3.26 ns t inhbidirpll 0.00 0.00 ns t outcobidirpll 0.50 2.25 0.50 2.99 ns t xzbidirpll 2.81 3.80 ns t zxbidirpll 2.81 3.80 ns table 103. ep20k1500e f max le timing microparameters symbol -1 speed grade -2 speed grade -3 speed grade unit min max min max min max t su 0.25 0.25 0.25 ns t h 0.25 0.25 0.25 ns t co 0.28 0.32 0.33 ns t lut 0.80 0.95 1.13 ns
110 altera corporation apex 20k programmable logic device family data sheet table 104. ep20k1500e f max esb timing microparameters symbol -1 speed grade -2 speed grade -3 speed grade unit min max min max min max t esbarc 1.78 2.02 1.95 ns t esbsrc 2.52 2.91 3.14 ns t esbawc 3.52 4.11 4.40 ns t esbswc 3.23 3.84 4.16 ns t esbwasu 0.62 0.67 0.61 ns t esbwah 0.41 0.55 0.55 ns t esbwdsu 0.77 0.79 0.81 ns t esbwdh 0.41 0.55 0.55 ns t esbrasu 1.74 1.92 1.85 ns t esbrah 0.00 0.01 0.23 ns t esbwesu 2.07 2.28 2.41 ns t esbweh 0.00 0.00 0.00 ns t esbdatasu 0.25 0.27 0.29 ns t esbdatah 0.13 0.13 0.13 ns t esbwaddrsu 0.11 0.04 0.11 ns t esbraddrsu 0.14 0.11 0.16 ns t esbdataco1 1.29 1.50 1.63 ns t esbdataco2 2.55 2.99 3.22 ns t esbdd 3.12 3.57 3.85 ns t pd 1.84 2.13 2.32 ns t ptermsu 1.08 1.19 1.32 ns t ptermco 1.31 1.53 1.66 ns table 105. ep20k1500e f max routing delays symbol -1 speed grade -2 speed grade -3 speed grade unit min max min max min max t f1-4 0.28 0.28 0.28 ns t f5-20 1.36 1.50 1.62 ns t f20+ 4.43 4.48 5.07 ns
altera corporation 111 apex 20k programmable logic device family data sheet table 106. ep20k1500e minimum pulse width timing parameters symbol -1 speed grade -2 speed grade -3 speed grade unit min max min max min max t ch 1.25 1.43 1.67 ns t cl 1.25 1.43 1.67 ns t clrp 0.20 0.20 0.20 ns t prep 0.20 0.20 0.20 ns t esbch 1.25 1.43 1.67 ns t esbcl 1.25 1.43 1.67 ns t esbwp 1.28 1.51 1.65 ns t esbrp 1.11 1.29 1.41 ns table 107. ep20k1500e external timing parameters symbol -1 speed grade -2 speed grade -3 speed grade unit min max min max min max t insu 3.09 3.30 3.58 ns t inh 0.00 0.00 0.00 ns t outco 2.00 6.18 2.00 6.81 2.00 7.36 ns t insupll 1.94 2.08 - ns t inhpll 0.00 0.00 - ns t outcopll 0.50 2.67 0.50 2.99 - - ns
112 altera corporation apex 20k programmable logic device family data sheet tables 109 and 110 show selectable i/o standard input and output delays for apex 20ke devices. if you select an i/o standard input or output delay other than lvcmos, ad d or subtract the selected speed grade to or from the lvcmos value. table 108. ep20k1500e external bidirectional timing parameters symbol -1 speed grade -2 speed grade -3 speed grade unit min max min max min max t insubidir 3.47 3.68 3.99 ns t inhbidir 0.00 0.00 0.00 ns t outcobidir 2.00 6.18 2.00 6.81 2.00 7.36 ns t xzbidir 6.91 7.62 8.38 ns t zxbidir 6.91 7.62 8.38 ns t insubidirpll 3.05 3.26 ns t inhbidirpll 0.00 0.00 ns t outcobidirpll 0.50 2.67 0.50 2.99 ns t xzbidirpll 3.41 3.80 ns t zxbidirpll 3.41 3.80 ns table 109. selectable i/o standard input delays symbol -1 speed grade -2 speed grade -3 speed grade unit min max min max min max min lvcmos 0.00 0.00 0.00 ns lvttl 0.00 0.00 0.00 ns 2.5 v 0.00 0.04 0.05 ns 1.8 v ?0.11 0.03 0.04 ns pci 0.01 0.09 0.10 ns gtl+ ?0.24 ?0.23 ?0.19 ns sstl-3 class i ?0.32 ?0.21 ?0.47 ns sstl-3 class ii ?0.08 0.03 ?0.23 ns sstl-2 class i ?0.17 ?0.06 ?0.32 ns sstl-2 class ii ?0.16 ?0.05 ?0.31 ns lvds ?0.12 ?0.12 ?0.12 ns ctt 0.00 0.00 0.00 ns agp 0.00 0.00 0.00 ns
altera corporation 113 apex 20k programmable logic device family data sheet power consumption to estimate device power consum ption, use the interactive power calculator on the altera web site at http://www.altera.com . configuration & operation the apex 20k architecture supports se veral configuration schemes. this section summarizes the device operating modes and available device configuration schemes. operating modes the apex architecture uses sram co nfiguration elements that require configuration data to be loaded each time the circuit powers up. the process of physically loading the sr am data into the device is called configuration. during initialization, which occurs immediately after configuration, the device resets regi sters, enables i/o pins, and begins to operate as a logic device. the i/o pi ns are tri-stated during power-up, and before and during configuratio n. together, the configuration and initialization processes are called command mode ; normal device operation is called user mode . before and during device configurat ion, all i/o pins are pulled to v ccio by a built-in weak pull-up resistor. table 110. selectable i/o standard output delays symbol -1 speed grade -2 speed grade -3 speed grade unit min max min max min max min lvcmos 0.00 0.00 0.00 ns lvttl 0.00 0.00 0.00 ns 2.5 v 0.00 0.09 0.10 ns 1.8 v 2.49 2.98 3.03 ns pci ?0.03 0.17 0.16 ns gtl+ 0.75 0.75 0.76 ns sstl-3 class i 1.39 1.51 1.50 ns sstl-3 class ii 1.11 1.23 1.23 ns sstl-2 class i 1.35 1.48 1.47 ns sstl-2 class ii 1.00 1.12 1.12 ns lvds ?0.48 ?0.48 ?0.48 ns ctt 0.00 0.00 0.00 ns agp 0.00 0.00 0.00 ns
114 altera corporation apex 20k programmable logic device family data sheet sram configuration elements allow apex 20k devices to be reconfigured in-circuit by loading new configuration data into the device. real-time reconfiguration is performed by forcing the device into command mode with a device pin, loading different configuration data, reinitializing the device, and resuming user- mode operation. in-field upgrades can be performed by distributing new configuration files. configuration schemes the configuration data for an apex 20k device can be loaded with one of five configur ation schemes (see table 111 ), chosen on the basis of the target application. an ep c2 or epc16 configuration device, intelligent controller, or the jtag port can be used to control the configuration of an apex 20k device. when a configuration device is used, the system can configure automatically at system power-up. multiple apex 20k devices can be configured in any of five configuration schemes by connecti ng the configuration enable ( nce ) and configuration enable output ( nceo ) pins on each device. f for more information on configuration, see application note 116 (configuring apex 20k, fl ex 10k, & flex 6000 devices.) device pin-outs see the altera web site (http://www.altera.com) or the altera digital library for pin-out information table 111. data sources for configuration configuration scheme data source configuration device epc1, epc2, epc16 configuration devices passive serial (ps) masterblas ter or byteblastermv download cable or serial data source passive parallel asynchronous (ppa) parallel data source passive parallel synchronous (pps) parallel data source jtag masterblaster or byteblasterm v download cable or a microprocessor with a jam or jbc file
altera corporation 115 apex 20k programmable logic device family data sheet revision history the information contained in the apex 20k programmab le logic device family data sheet version 5.1 supersedes information published in previous versions. version 5.1 apex 20k programmable logic device family data sheet version 5.1 contains the following changes: in version 5.0, the vi input voltage spec was updated in table 28 on page 63. in version 5.0, note (5) to tables 27 through 30 was revised. added note (2) to figure 21 on page 33 . version 5.0 apex 20k programmable logic device family data sheet version 5.0 contains the following changes: updated tables 23 through 26 . removed 2.5-v operating condition tables because all apex 20k de vices are now 5.0-v tolerant. updated conditions in tables 33 , 38 and 39 . updated data for t esbdatah parameter. version 4.3 apex 20k programmable logic device family data sheet version 4.3 contains the following changes: updated figure 20 . updated note (2) to table 13 . updated notes to tables 27 through 30 . version 4.2 apex 20k programmable logic device family data sheet version 4.2 contains the following changes: updated figure 29 . updated note (1) to figure 29 .
116 altera corporation apex 20k programmable logic device family data sheet version 4.1 apex 20k programmable logic device family data sheet version 4.1 contains the following changes: t esbweh added to figure 37 and tables 35 , 50 , 56 , 62 , 68 , 74 , 86 , 92 , 97 , and 104 . updated ep20k300e device inte rnal and external timing numbers in tables 79 through 84 .
copyright ? 2004 altera corporation. all rights reserv ed. altera, the programmable solutions company, the stylized altera logo, specific de vice designations, and all other wo rds and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of altera corporation in the u.s. and other co untries. all other product or service names are the property of their respective holders. altera products are protected under numerous u.s. and fo reign patents and pending applications, mask work rights, and copyrights. altera warrants perfor mance of its semi conductor products to current specifications in accordance with altera?s standard warranty, but reserves the right to make changes to any products and services at any time wi thout notice. altera assumes no responsibility or liability arising out of the application or use of any inform ation, product, or service described herein except as expressly agreed to in writing by alte ra corporation. altera customers are advised to obtain the latest vers ion of device specific ations before relying on any published information and before placing orders for products or services. 101 innovation drive san jose, ca 95134 (408) 544-7000 http://www.altera.com applications hotline : (800) 800-epld customer marketing: (408) 544-7104 literature services: lit_req@altera.com apex 20k programmable logic device family data sheet 117 altera corporation

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